Santiago Asuncion

According to our database, Santiago Asuncion authored at least 4 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies.

Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2018

An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS.

Kevin Zheng, Yohan Frans, Sai Lalith Ambatipudi, Santiago Asuncion, Hari Teja Reddy, Ken Chang, Boris Murmann

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET.

Yohan Frans, Jaewook Shin, Lei Zhou, Parag Upadhyaya, Jay Im, Vassili Kireev, Mohamed Elzeftawi, Hiva Hedayati, Toan Pham, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang

IEEE J. Solid State Circuits, 2017

2016

A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET.

Yohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016