Seyed Mohammad Ali Zeinolabedin
Orcid: 0000-0002-9156-3751
According to our database1,
Seyed Mohammad Ali Zeinolabedin
authored at least 22 papers
between 2014 and 2023.
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Bibliography
2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI.
IEEE Trans. Biomed. Circuits Syst., 2022
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
2021
IEEE Des. Test, 2021
Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
2019
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2019
2016
A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Circuits Syst. Signal Process., 2016
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm<sup>2</sup> per channel in 65-nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm<sup>2</sup> per Channel in 65-nm CMOS.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
An area- and power-efficient FIFO with error-reduced data compression for image/video processing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014