Yatin Hoskote

According to our database, Yatin Hoskote authored at least 10 papers between 2007 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS.

Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2015

Learning-Based Power Modeling of System-Level Black-Box IPs.

Dongwook Lee, Taemin Kim, Kyungtae Han, Yatin Hoskote, Lizy K. John, Andreas Gerstlauer

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Design of a low power SoC testchip for wearables and IoTs.

May Wu, Ravi Iyer, Yatin Hoskote, Steven Zhang, Julio Zamora-Esquivel, German Fabila Garcia, Ilya Klotchkov, Mukesh Bhartiya

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2014

High level design for wearables and IoT.

Yatin Hoskote, Ilya Klotchkov

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Automatic generation of custom SIMD instructions for Superword Level Parallelism.

Taemin Kim, Yatin Hoskote

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Edit distance based instruction merging technique to improve flexibility of custom instructions toward flexible accelerator design.

Hui Huang, Taemin Kim, Yatin Hoskote

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Keynote talk II: Designing tomorrow's chips.

Yatin Hoskote

Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

2007

A 5-GHz Mesh Interconnect for a Teraflops Processor.

Yatin Hoskote, Sriram R. Vangal, Arvind P. Singh, Nitin Borkar, Shekhar Borkar

IEEE Micro, 2007

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS.

Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Priya Iyer, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.

James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007