Simha Sethumadhavan

Orcid: 0000-0002-6180-7153

Affiliations:
  • Columbia University, New York City, USA


According to our database1, Simha Sethumadhavan authored at least 81 papers between 2003 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Guest Editorial: IEEE Transactions on Computer, Special Issue on Hardware Security.
IEEE Trans. Computers, February, 2023

Revisiting Residue Codes for Modern Memories.
IEEE Micro, 2023

Architectural Security Regulation.
IEEE Comput. Archit. Lett., 2023

How Much is Performance Worth to Users?
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022
How Much is Performance Worth to Users? A Quantitative Approach.
CoRR, 2022

Timeloops: System Call Policy Learning for Containerized Microservices.
CoRR, 2022

COMMAND: Certifiable Open Measurable Mandates.
CoRR, 2022

2021
MUSE: Multi-Use Error Correcting Codes.
CoRR, 2021

CRYLOGGER: Detecting Crypto Misuses Dynamically.
Proceedings of the 42nd IEEE Symposium on Security and Privacy, 2021

EPI: Efficient Pointer Integrity For Securing Embedded Systems.
Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

Towards Zero Trust: An Experience Report.
Proceedings of the IEEE Secure Development Conference, 2021

ZeRØ: Zero-Overhead Resilient Operation Under Pointer Integrity Attacks.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

No-FAT: Architectural Support for Low Overhead Memory Safety Checks.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

HARDROID: Transparent Integration of Crypto Accelerators in Android.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

2020
SPAM: Stateless Permutation of Application Memory.
CoRR, 2020

A New Doctrine for Hardware Security.
CoRR, 2020

WaC: A New Doctrine for Hardware Security.
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020

2019
Secure Architectures.
IEEE Micro, 2019

PAIRS: Control Flow Protection using Phantom Addressed Instructions.
CoRR, 2019

Practical Byte-Granular Memory Blacklisting using Califorms.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Heterogeneous Isolated Execution for Commodity GPUs.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Motivating Security-Aware Energy Management.
IEEE Micro, 2018

Corrections to "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time".
IEEE J. Solid State Circuits, 2018

Blacklist Core: Machine-Learning Based Dynamic Operating-Performance-Point Blacklisting for Mitigating Power-Management Security Attacks.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Practical Memory Safety with REST.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

A Case Study in Analog Co-Processing for Solving Stochastic Differential Equations.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

2017
Analog Computing in a Modern Context: A Linear Algebra Accelerator Case Study.
IEEE Micro, 2017

FIRED: Frequent Inertial Resets with Diversification for Emerging Commodity Cyber-Physical Systems.
CoRR, 2017

Heavy Tails in Program Structure.
IEEE Comput. Archit. Lett., 2017

CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management.
Proceedings of the 26th USENIX Security Symposium, 2017

Hybrid analog-digital solution of nonlinear partial differential equations.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Why do programs have heavy tails?
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Reviving instruction set randomization.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

2016
Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time.
IEEE J. Solid State Circuits, 2016

Hardware-Enforced Privacy.
Computer, 2016

Security Implications of Third-Party Accelerators.
IEEE Comput. Archit. Lett., 2016

Hardware Enforced Statistical Privacy.
IEEE Comput. Archit. Lett., 2016

Code relatives: detecting similarly behaving software.
Proceedings of the 24th ACM SIGSOFT International Symposium on Foundations of Software Engineering, 2016

Identifying functionally similar code in complex codebases.
Proceedings of the 24th IEEE International Conference on Program Comprehension, 2016

Evaluation of an Analog Accelerator for Linear Algebra.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

RoboBench: Towards sustainable robotics system benchmarking.
Proceedings of the 2016 IEEE International Conference on Robotics and Automation, 2016

2015
Making Lock-free Data Structures Verifiable with Artificial Transactions.
ACM SIGOPS Oper. Syst. Rev., 2015

The Spy in the Sandbox - Practical Cache Attacks in Javascript.
CoRR, 2015

Trustworthy hardware from untrusted components.
Commun. ACM, 2015

Increasing reconfigurability with memristive interconnects.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A silicon anti-virus engine.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Continuous-time hybrid computation with programmable nonlinearities.
Proceedings of the ESSCIRC Conference 2015, 2015

Heisenbyte: Thwarting Memory Disclosure Attacks using Destructive Code Reads.
Proceedings of the 22nd ACM SIGSAC Conference on Computer and Communications Security, 2015

The Spy in the Sandbox: Practical Cache Attacks in JavaScript and their Implications.
Proceedings of the 22nd ACM SIGSAC Conference on Computer and Communications Security, 2015

2014
Guest Editorial: Robust and energy-secure systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Unsupervised Anomaly-Based Malware Detection Using Hardware Features.
Proceedings of the Research in Attacks, Intrusions and Defenses, 2014

A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
A Quantitative, Experimental Approach to Measuring Processor Side-Channel Security.
IEEE Micro, 2013

Practical, Lightweight Secure Inclusion of Third-Party Intellectual Property.
IEEE Des. Test, 2013

On the feasibility of online malware detection with performance counters.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

WHISK: An uncore architecture for Dynamic Information Flow Tracking in heterogeneous embedded SoCs.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

FANCI: identification of stealthy malicious logic using boolean functional analysis.
Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, 2013

2012
Approximate graph clustering for program characterization.
ACM Trans. Archit. Code Optim., 2012

A Case for Hybrid Discrete-Continuous Architectures.
IEEE Comput. Archit. Lett., 2012

TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Side-channel vulnerability factor: A metric for measuring information leakage.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

The MEERKATS Cloud Security Architecture.
Proceedings of the 32nd International Conference on Distributed Computing Systems Workshops (ICDCS 2012 Workshops), 2012

Concurrency Attacks.
Proceedings of the 4th USENIX Workshop on Hot Topics in Parallelism, 2012

Hardware enhanced security.
Proceedings of the ACM Conference on Computer and Communications Security, 2012

2011
Silencing Hardware Backdoors.
Proceedings of the 32nd IEEE Symposium on Security and Privacy, 2011

Rapid identification of architectural bottlenecks via precise event counting.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

The SPARCHS Project: Hardware Support for Software Security.
Proceedings of the First SysSec Workshop 2011, 2011

Distributed Storage of Large-Scale Multidimensional Electroencephalogram Data Using Hadoop and HBase.
Proceedings of the Grid and Cloud Database Management, 2011

2010
Tamper Evident Microprocessors.
Proceedings of the 31st IEEE Symposium on Security and Privacy, 2010

2009
Composable Multicore Chips.
Proceedings of the Multicore Processors and Systems, 2009

COMPASS: A Community-driven Parallelization Advisor for Sequential Software.
Proceedings of the 2009 ICSE Workshop on Multicore Software Engineering, 2009

2008
Multitasking workload scheduling on flexible core chip multiprocessors.
SIGARCH Comput. Archit. News, 2008

2007
Composable Lightweight Processors.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Late-binding: enabling unordered load-store queues.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Design and Implementation of the TRIPS Primary Memory System.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2004
Scalable Hardware Memory Disambiguation for High-ILP Processors.
IEEE Micro, 2004

Scalable selective re-execution for EDGE architectures.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2003
Pagerank Computation and Keyword Search on Distributed Systems and P2P Networks.
J. Grid Comput., 2003

Compiler Directed Parallelization of Loops in Scale for Shared-Memory Multiprocessors.
Proceedings of the Computational Science - ICCS 2003, 2003

Distributed Pagerank for P2P Systems.
Proceedings of the 12th International Symposium on High-Performance Distributed Computing (HPDC-12 2003), 2003


  Loading...