Shien-Chun Luo
According to our database1,
Shien-Chun Luo
authored at least 13 papers
between 2007 and 2022.
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Bibliography
2022
Configurable Deep Learning Accelerator with Bitwise-accurate Training and Verification.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2010
A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
2009
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics.
IEEE Trans. Very Large Scale Integr. Syst., 2009
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007