Nathaniel Ross Pinckney

According to our database1, Nathaniel Ross Pinckney authored at least 24 papers between 2007 and 2020.

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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.
IEEE J. Solid State Circuits, 2020

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

MAGNet: A Modular Accelerator Generator for Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor.
IEEE J. Solid State Circuits, 2018

Impact of FinFET on Near-Threshold Voltage Scalability.
IEEE Des. Test, 2017

8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Supply boosting for high-performance processors in flip-chip packages.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability.
Proceedings of the 53rd Annual Design Automation Conference, 2016

A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple.
Proceedings of the Symposium on VLSI Circuits, 2015

Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Limits of Parallelism and Boosting in Dim Silicon.
IEEE Micro, 2013

Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction.
IEEE J. Solid State Circuits, 2013

A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Swizzle-Switch Networks for Many-Core Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Bubble Razor: An architecture-independent approach to timing-error detection and correction.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Assessing the performance limits of parallelized near-threshold computing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

A MIPS R2000 implementation.
Proceedings of the 45th Design Automation Conference, 2008

Parallelized radix-4 scalable montgomery multipliers.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007