Siying Feng

According to our database, Siying Feng authored at least 14 papers between 2017 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher.

Yichen Yang, Jingtao Li, Nishil Talati, Subhankar Pal, Siying Feng, Chaitali Chakrabarti, Trevor N. Mudge, Ronald G. Dreslinski

CoRR, 2023

2022

A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.

Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows.

Siying Feng, Xin He, Kuan-Yu Chen, Liu Ke, Xuan Zhang, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor.

Xin He, Kuan-Yu Chen, Siying Feng, Hun-Seok Kim, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021

SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.

Subhankar Pal, Aporva Amarnath, Siying Feng, Michael F. P. O'Boyle, Ronald G. Dreslinski, Christophe Dubach

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics.

Siying Feng, Jiawen Sun, Subhankar Pal, Xin He, Kuba Kaszyk, Dong-Hyeon Park, John Magnus Morton, Trevor N. Mudge, Murray Cole, Michael F. P. O'Boyle, Chaitali Chakrabarti, Ronald G. Dreslinski

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.

Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski

IEEE J. Solid State Circuits, 2020

HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework.

Subhankar Pal, Kuba Kaszyk, Siying Feng, Björn Franke, Murray Cole, Michael F. P. O'Boyle, Trevor N. Mudge, Ronald G. Dreslinski

Proceedings of the IEEE International Symposium on Workload Characterization, 2020

Sparse-TPU: adapting systolic arrays for sparse matrices.

Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Kuan-Yu Chen, Ronald G. Dreslinski, Trevor N. Mudge

Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.

Subhankar Pal, Siying Feng, Dong-Hyeon Park, Sung Kim, Aporva Amarnath, Chi-Sheng Yang, Xin He, Jonathan Beaumont, Kyle May, Yan Xiong, Kuba Kaszyk, John Magnus Morton, Jiawen Sun, Michael F. P. O'Boyle, Murray Cole, Chaitali Chakrabarti, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski

Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.

Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective.

Siying Feng, Subhankar Pal, Yichen Yang, Ronald G. Dreslinski

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

2018

OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.

Subhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

A carbon nanotube transistor based RISC-V processor using pass transistor logic.

Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017