Subhankar Pal

Orcid: 0000-0002-1564-7443

According to our database¹, Subhankar Pal authored at least 27 papers between 2014 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Article

PhD thesis

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Bibliography

2023

Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher.

[BibT_eX]

[DOI]

CoRR, 2023

xURLCC in 6g with meshed RAN.

[BibT_eX]

[DOI]

Mohammad Ali Khoshkholghi

CoRR, 2023

Efficient Pruning for Machine Learning Under Homomorphic Encryption.

[BibT_eX]

[DOI]

Proceedings of the Computer Security - ESORICS 2023, 2023

2022

OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators.

[BibT_eX]

[DOI]

Subhankar Pal

Swagath Venkataramani

Viji Srinivasan

Kailash Gopalakrishnan

ACM Trans. Embed. Comput. Syst., November, 2022

Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A Holistic Solution for Reliability of 3D Parallel Systems.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

HE-PEx: Efficient Machine Learning under Homomorphic Encryption using Pruning, Permutation and Expansion.

[BibT_eX]

[DOI]

CoRR, 2022

HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs.

[BibT_eX]

[DOI]

CoRR, 2022

2021

Towards Closing the Programmability-Efficiency Gap using Software-Defined Hardware.

[BibT_eX]

[DOI]

Subhankar Pal

PhD thesis, 2021

Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles.

[BibT_eX]

[DOI]

Ronald Dreslinski Jr.

Pradip Bose

IEEE Comput. Archit. Lett., 2021

Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.

[BibT_eX]

[DOI]

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.

[BibT_eX]

[DOI]

Subhankar Pal

Aporva Amarnath

Siying Feng

Michael F. P. O'Boyle

Ronald G. Dreslinski

Christophe Dubach

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators.

[BibT_eX]

[DOI]

Subhankar Pal

Swagath Venkataramani

Viji Srinivasan

Kailash Gopalakrishnan

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics.

[BibT_eX]

[DOI]

Michael F. P. O'Boyle

Chaitali Chakrabarti

Ronald G. Dreslinski

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.

[BibT_eX]

[DOI]

Michael Bedford Taylor

IEEE J. Solid State Circuits, 2020

STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.

[BibT_eX]

[DOI]

CoRR, 2020

Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework.

[BibT_eX]

[DOI]

Michael F. P. O'Boyle

Trevor N. Mudge

Ronald G. Dreslinski

Proceedings of the IEEE International Symposium on Workload Characterization, 2020

Sparse-TPU: adapting systolic arrays for sparse matrices.

[BibT_eX]

[DOI]

Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

R2D3: A Reliability Engine for 3D Parallel Systems.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.

[BibT_eX]

[DOI]

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

2018

OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

A carbon nanotube transistor based RISC-V processor using pass transistor logic.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2014

A New Design of an N-Bit Reversible Arithmetic Logic Unit.

[BibT_eX]

[DOI]

Subhankar Pal

Chetan Vudadha

P. Sai Phaneendra

Sreehari Veeramachaneni

Srinivas B. Mandalika

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

Subhankar Pal

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