Aporva Amarnath
Orcid: 0000-0002-5345-2022
According to our database1,
Aporva Amarnath authored at least 27 papers
between 2017 and 2026.
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Bibliography
2026
EPOCHS-1: A 12 nm Highly Heterogeneous Open-Source SoC With Distributed Coin-Based Power Management and Integrated Hybrid Voltage Regulation.
IEEE J. Solid State Circuits, May, 2026
2025
CoRR, March, 2025
Proceedings of the Eighth Conference on Machine Learning and Systems, 2025
FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
ARTEMIS: Agile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous Era.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
No Time to Lose: Enabling Real-Time Fluorescence Lifetime Imaging on Resource-constrained FPGAs Through Efficient Scheduling.
Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2025
2024
Unlocking Real-Time Fluorescence Lifetime Imaging: Multi-Pixel Parallelism for FPGA-Accelerated Processing.
CoRR, 2024
Compressing Recurrent Neural Networks for FPGA-accelerated Implementation in Fluorescence Lifetime Imaging.
CoRR, 2024
A Neuro-Symbolic Approach to Multi-Agent RL for Interpretability and Probabilistic Decision Making.
CoRR, 2024
IEEE Comput. Archit. Lett., 2024
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
ACM J. Emerg. Technol. Comput. Syst., 2022
CoRR, 2022
2021
A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors.
ACM J. Emerg. Technol. Comput. Syst., 2021
IEEE Comput. Archit. Lett., 2021
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
2020
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits, 2020
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.
CoRR, 2020
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
2019
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
2018
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017