Aporva Amarnath

Orcid: 0000-0002-5345-2022

According to our database¹, Aporva Amarnath authored at least 18 papers between 2017 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

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On csauthors.net:

Bibliography

2024

A Neuro-Symbolic Approach to Multi-Agent RL for Interpretability and Probabilistic Decision Making.

[BibT_eX]

[DOI]

Sarathkrishna Swaminathan

Ryan Riegel

Alexander Gray

CoRR, 2024

14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

A Holistic Solution for Reliability of 3D Parallel Systems.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs.

[BibT_eX]

[DOI]

CoRR, 2022

2021

A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles.

[BibT_eX]

[DOI]

Ronald Dreslinski Jr.

Pradip Bose

IEEE Comput. Archit. Lett., 2021

SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.

[BibT_eX]

[DOI]

Subhankar Pal

Aporva Amarnath

Siying Feng

Michael F. P. O'Boyle

Ronald G. Dreslinski

Christophe Dubach

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.

[BibT_eX]

[DOI]

Michael Bedford Taylor

IEEE J. Solid State Circuits, 2020

STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.

[BibT_eX]

[DOI]

CoRR, 2020

Sparse-TPU: adapting systolic arrays for sparse matrices.

[BibT_eX]

[DOI]

Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

R2D3: A Reliability Engine for 3D Parallel Systems.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.

[BibT_eX]

[DOI]

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.

[BibT_eX]

[DOI]

IEEE Micro, 2018

OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

A carbon nanotube transistor based RISC-V processor using pass transistor logic.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Aporva Amarnath

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