Tifenn Hirtzlin
Orcid: 0000-0002-6931-6930
According to our database1,
Tifenn Hirtzlin
authored at least 30 papers
between 2017 and 2023.
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Bibliography
2023
Powering AI at the Edge: A Robust, Memristor-based Binarized Neural Network with Near-Memory Computing and Miniaturized Solar Cell.
CoRR, 2023
1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation.
Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy.
Adv. Intell. Syst., 2022
Hardware calibrated learning to compensate heterogeneity in analog RRAM-based Spiking Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing.
Proceedings of the IEEE International Memory Workshop, 2022
Frequency modulation of conductance level in PCM device for neuromorphic applications.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks.
CoRR, 2021
CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
2020
Digital Implementation of Neuromorphic systems using Emerging Memory devices. (Conception de circuits neuromorphiques numériques exploitant des nano-composants émergents).
PhD thesis, 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays.
CoRR, 2019
CoRR, 2019
In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks.
CoRR, 2019
IEEE Access, 2019
Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
Circuit-Level Evaluation of the Generation of Truly Random Bits with Superparamagnetic Tunnel Junctions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the 2017 19th International Conference on Transparent Optical Networks (ICTON), 2017