Niccolo Castellani
According to our database1,
Niccolo Castellani
authored at least 27 papers
between 2014 and 2023.
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Bibliography
2023
1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation.
Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023
Investigation of resistance fluctuations in ReRAM: physical origin, temporal dependence and impact on memory reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Integration of HfO2-based 3D OxRAM with GAA stacked-nanosheet transistor for high-density embedded memory.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy.
Adv. Intell. Syst., 2022
Hardware calibrated learning to compensate heterogeneity in analog RRAM-based Spiking Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Multilayer Deposition in Phase-Change Memory for Best Endurance Performance and Reduced Bit Error Rate.
Proceedings of the IEEE International Memory Workshop, 2022
Proceedings of the IEEE International Memory Workshop, 2022
1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing.
Proceedings of the IEEE International Memory Workshop, 2022
Proceedings of the IEEE International Memory Workshop, 2022
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
Multilayer Structure in SeAsGeSi-based OTS for High Thermal Stability and Reliability Enhancement.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
2021
Ex Situ Transfer of Bayesian Neural Networks to Resistive Memory-Based Inference Hardware.
Adv. Intell. Syst., 2021
Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the IEEE International Memory Workshop, 2021
Multilayer OTS Selectors Engineering for High Temperature Stability, Scalability and High Endurance.
Proceedings of the IEEE International Memory Workshop, 2021
16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors.
Proceedings of the IEEE International Memory Workshop, 2021
2020
In-situ learning harnessing intrinsic resistive memory variability through Markov Chain Monte Carlo Sampling.
CoRR, 2020
2018
Carbon electrode for Ge-Se-Sb based OTS selector for ultra low leakage current and outstanding endurance.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Metal Oxide Resistive Memory (OxRAM) and Phase Change Memory (PCM) as Artificial Synapses in Spiking Neural Networks.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017
2014
PhD thesis, 2014
Proceedings of the 44th European Solid State Device Research Conference, 2014