Joseph S. Friedman

Orcid: 0000-0001-9847-4455

According to our database1, Joseph S. Friedman authored at least 55 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Magnetic skyrmions and domain walls for logical and neuromorphic computing.
Neuromorph. Comput. Eng., June, 2023

Deep Neuromorphic Networks with Superconducting Single Flux Quanta.
CoRR, 2023

Neuromorphic Hebbian learning with magnetic tunnel junction synapses.
CoRR, 2023

Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe2 Thin Film Transistors.
CoRR, 2023

Near-Landauer Reversible Skyrmion Logic with Voltage-Based Propagation.
CoRR, 2023

Roadmap for Unconventional Computing with Nanotechnology.
CoRR, 2023

A T-depth two Toffoli gate for 2D square lattice architectures.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

2022
Efficient Quantum Circuit Design with a Standard Cell Approach.
CoRR, 2022

Logical and Physical Reversibility of Conservative Skyrmion Logic.
CoRR, 2022

Intrinsic Lateral Inhibition Facilitates Winner-Take-All in Domain Wall Racetrack Arrays for Neuromorphic Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Purely Spintronic Leaky Integrate-and-Fire Neurons.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic Circuits.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Hybrid Pass Transistor Logic With Ambipolar Transistors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Karnaugh Map Method for Memristive and Spintronic Asymmetric Basis Logic Functions.
IEEE Trans. Computers, 2021

Energy efficiency challenges for all-spin logic.
Microelectron. J., 2021

Synchronous Unsupervised STDP Learning with Stochastic STT-MRAM Switching.
CoRR, 2021

Experimental Demonstration of Neuromorphic Network with STT MTJ Synapses.
CoRR, 2021

Shape-Dependent Multi-Weight Magnetic Artificial Synapses for Neuromorphic Computing.
CoRR, 2021

High-Speed CMOS-Free Purely Spintronic Asynchronous Recurrent Neural Network.
CoRR, 2021

Frustrated Arrays of Nanomagnets for Efficient Reservoir Computing.
CoRR, 2021

Skyrmion Logic Clocked via Voltage Controlled Magnetic Anisotropy.
CoRR, 2021

Controllable reset behavior in domain wall-magnetic tunnel junction artificial neurons for task-adaptable computation.
CoRR, 2021

Fast Swapping in a Quantum Multiplier Modelled as a Queuing Network.
Proceedings of the Reversible Computation - 13th International Conference, 2021

Secure Logic Locking with Strain-Protected Nanomagnet Logic.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Domain Wall Leaky Integrate-and-Fire Neurons with Shape-Based Configurable Activation Functions.
CoRR, 2020

Threshold Logic with Current-Driven Magnetic Domain Walls.
CoRR, 2020

Unsupervised Competitive Hardware Learning Rule for Spintronic Clustering Architecture.
CoRR, 2020

Reservoir Computing with Planar Nanomagnet Arrays.
CoRR, 2020

Hybrid Pass Transistor Logic with Dual-Gate Ambipolar CNTFETs.
CoRR, 2020

CMOS-Free Multilayer Perceptron Enabled by Four-Terminal MTJ Device.
CoRR, 2020

Device Modeling and Circuit Design for Scalable Beyond-CMOS Computing.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Process Variation Model and Analysis for Domain Wall-Magnetic Tunnel Junction Logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

CMOS-Free Magnetic Domain Wall Leaky Integrate-and-Fire Neurons with Intrinsic Lateral Inhibition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Plasticity-Enhanced Domain-Wall MTJ Neural Networks for Energy-Efficient Online Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Overhead Requirements for Stateful Memristor Logic.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Exploiting Dual-Gate Ambipolar CNFETs for Scalable Machine Learning Classification.
CoRR, 2019

Shape-based Magnetic Domain Wall Drift for an Artificial Spintronic Leaky Integrate-and-Fire Neuron.
CoRR, 2019

Toggle Spin-Orbit Torque MRAM with Perpendicular Magnetic Anisotropy.
CoRR, 2019

2018
Conservative Skyrmion Logic System.
CoRR, 2018

Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Circuit-Level Evaluation of the Generation of Truly Random Bits with Superparamagnetic Tunnel Junctions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

All-Carbon Spin Logic Sensor for RRAM Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Approximation enhancement for stochastic Bayesian inference.
Int. J. Approx. Reason., 2017

Transient model with interchangeability for dual-gate ambipolar CNTFET logic design.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Closed-form model for dual-gate ambipolar CNTFET circuit design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Bayesian Inference With Muller C-Elements.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Sleep stage classification with stochastic Bayesian inference.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

2015
Emitter-Coupled Spin-Transistor Logic: Cascaded Spintronic Computing Beyond 10 GHz.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Magnetoresistance implications for complementary magnetic tunnel junction logic (CMAT).
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Enhanced Spin-Diode Synthesis Using Logic Sharing.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Spintronic devices as key elements for energy-efficient neuroinspired architectures.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Emitter-coupled spin-transistor logic.
J. Parallel Distributed Comput., 2014

2013
Spin diode network synthesis using functional composition.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

2012
Emitter-coupled spin-transistor logic.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

InMnAs magnetoresistive spin-diode logic.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012


  Loading...