François Andrieu

According to our database1, François Andrieu authored at least 40 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Powering AI at the Edge: A Robust, Memristor-based Binarized Neural Network with Near-Memory Computing and Miniaturized Solar Cell.
CoRR, 2023

1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation.
Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023

Investigation of resistance fluctuations in ReRAM: physical origin, temporal dependence and impact on memory reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Reliability assessment of hafnia-based ferroelectric devices and arrays for memory and AI applications (Invited).
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Memory Window in Si: HfO2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced Nodes.
Proceedings of the IEEE International Memory Workshop, 2023

Integration of HfO2-based 3D OxRAM with GAA stacked-nanosheet transistor for high-density embedded memory.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

Binary ReRAM-based BNN first-layer implementation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Hardware calibrated learning to compensate heterogeneity in analog RRAM-based Spiking Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Multilayer Deposition in Phase-Change Memory for Best Endurance Performance and Reduced Bit Error Rate.
Proceedings of the IEEE International Memory Workshop, 2022



A novel 3D 1T1R RRAM architecture for memory-centric Hyperdimensional Computing.
Proceedings of the IEEE International Memory Workshop, 2022

TiTe/Ge2Sb2Te5Bi-layer-based Phase-Change Memory Targeting Storage Class Memory.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

Multilayer Structure in SeAsGeSi-based OTS for High Thermal Stability and Reliability Enhancement.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

Enhanced Thermal Confinement in Phase-Change Memory Targeting Current Reduction.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

Frequency modulation of conductance level in PCM device for neuromorphic applications.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

Interplay between charge trapping and polarization switching in MFDM stacks evidenced by frequency-dependent measurements.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2020
Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications.
CoRR, 2020

2018
A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2017
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017


2016


Impact of intermediate BEOL technology on standard cell performances of 3D VLSI.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
Performance and reliability of strained SOI transistors for advanced planar FDSOI technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Variability of planar Ultra-Thin Body and Buried oxide (UTBB) FDSOI MOSFETs.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

CMOS VT characterization by capacitance measurements in FDSOI PIN gated diodes.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Superior performance and Hot Carrier reliability of Strained FDSOI nMOSFETs for advanced CMOS technology nodes.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Why are SCE overestimated in FD-SOI MOSFETs?
Proceedings of the European Solid-State Device Research Conference, 2013

Threshold voltage extraction techniques and temperature effect in context of global variability in UTBB mosfets.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below.
J. Low Power Electron., 2012

Multibranch mobility characterization: Evidence of carrier mobility enhancement by back-gate biasing in FD-SOI MOSFET.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2010
32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009


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