Toshihiko Himeno

According to our database, Toshihiko Himeno authored at least 4 papers between 1997 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

A 113mm2 32Gb 3b/cell NAND flash memory.

Takuya Futatsuyama, Norihiro Fujita, Naoya Tokiwa, Yoshihiko Shindo, Toshiaki Edahiro, Teruhiko Kamei, Hiroaki Nasu, Makoto Iwai, Koji Kato, Yasuyuki Fukuda, Naoaki Kanagawa, Naofumi Abiko, Masahide Matsumoto, Toshihiko Himeno, Toshifumi Hashimoto, Yi-Ching Liu, Hardwell Chibvongodze, Takamitsu Hori, Manabu Sakai, Hong Ding, Yoshiharu Takeuchi, Hitoshi Shiga, Norifumi Kajimura, Yasuyuki Kajitani, Kiyofumi Sakurai, Kosuke Yanagidaira, Toshihiro Suzuki, Yuko Namiki, Tomofumi Fujimura, Man Mui, Hao Nguyen, Seungpil Lee, Alex Mak, Jeffery Lutze, Tooru Maruyama, Toshiharu Watanabe, Takahiko Hara, Shigeo Ohshima

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2002

A 125-mm² 1-Gb NAND flash memory with 10-MByte/s program speed.

Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian J. Che

IEEE J. Solid State Circuits, 2002

1999

A 130-mm/², 256-Mbit NAND flash with shallow trench isolation technology.

Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui

IEEE J. Solid State Circuits, 1999

1997

A 120-mm² 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed.

Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto

IEEE J. Solid State Circuits, 1997