Kang-Deog Suh
According to our database1,
Kang-Deog Suh
authored at least 12 papers
between 1995 and 2010.
Collaborative distances:
Collaborative distances:
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Bibliography
2010
Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories.
IEEE J. Solid State Circuits, 2010
IEICE Trans. Electron., 2010
2003
IEEE J. Solid State Circuits, 2003
2002
IEEE J. Solid State Circuits, 2002
2001
A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes.
IEEE J. Solid State Circuits, 2001
2000
A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit.
IEEE J. Solid State Circuits, 2000
A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme.
IEEE J. Solid State Circuits, 2000
1998
An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS).
IEEE J. Solid State Circuits, 1998
1997
A 120-mm<sup>2</sup> 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed.
IEEE J. Solid State Circuits, 1997
A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology.
IEEE J. Solid State Circuits, 1997
1996
A 117-mm<sup>2</sup> 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications.
IEEE J. Solid State Circuits, 1996
1995
IEEE J. Solid State Circuits, November, 1995