Yasuko Eckert

According to our database1, Yasuko Eckert authored at least 16 papers between 2012 and 2023.

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Bibliography

2023

2021
Accelerating Variational Quantum Algorithms Using Circuit Concurrency.
CoRR, 2021

DUB: dynamic underclocking and bypassing in nocs for heterogeneous GPU workloads.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021

Analyzing and Leveraging Decoupled L1 Caches in GPUs.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
Experiences with ML-Driven Design: A NoC Case Study.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Analyzing and Leveraging Shared L1 Caches in GPUs.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2018
CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems.
ACM Trans. Archit. Code Optim., 2018

Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques.
CoRR, 2018

2017
CODA: Enabling Co-location of Computation and Data for Near-Data Processing.
CoRR, 2017


2016
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism.
CoRR, 2016

Prefetching Techniques for Near-memory Throughput Processors.
Proceedings of the 2016 International Conference on Supercomputing, 2016

2015
Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

2014
A comparison of core power gating strategies implemented in modern hardware.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Increasing TLB reach by exploiting clustering in page translations.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2012
Something old and something new: P-states can borrow microarchitecture techniques too.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012


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