Uday Mallappa

Orcid: 0000-0003-3061-9392

According to our database1, Uday Mallappa authored at least 11 papers between 2018 and 2023.

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Bibliography

2023
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.
ACM Trans. Design Autom. Electr. Syst., July, 2023

2022
Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.
IEEE Embed. Syst. Lett., 2022

JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.
IEEE Des. Test, 2022

TermiNETor: Early Convolution Termination for Efficient Deep Neural Networks.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

RLPlace: Deep RL Guided Heuristics for Detailed Placement Optimization.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

PatterNet: explore and exploit filter patterns for efficient deep neural networks.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
GRA-LPO: Graph Convolution Based Leakage Power Optimization.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
"Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018


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