Bangqi Xu

Orcid: 0000-0001-6768-6201

Affiliations:
  • University of California, San Diego, CA, USA


According to our database1, Bangqi Xu authored at least 14 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2022
TritonRoute-WXL: The Open-Source Router With Integrated DRC Engine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2021

TritonRoute: The Open-Source Detailed Router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020
The Tao of PAO: Anatomy of a Pin Access Oracle for Detailed Routing.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2019 CAD Contest: LEF/DEF Based Global Routing.
Proceedings of the International Conference on Computer-Aided Design, 2019

Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Learning-based prediction of package power delivery network quality.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
TritonRoute: an initial detailed router for advanced VLSI technologies.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
The architecture value engine: measuring and delivering sustainable SoC improvement.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016


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