Kim Grüttner

Orcid: 0000-0002-4988-3858

According to our database1, Kim Grüttner authored at least 90 papers between 2005 and 2023.

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Bibliography

2023
The Universal Safety Format in Action: Tool Integration and Practical Application.
SN Comput. Sci., March, 2023

Teaching Cyber-Physical Systems in Student Project Groups.
Proceedings of the Software Engineering im Unterricht der Hochschulen, 2023

Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms.
Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023

RISC-V Timing-Instructions for Open Time-Triggered Architectures.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

A RISC-V based platform supporting mixed timing-critical and high performance workloads.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

Universal Safety Format: Automated Safety Software Generation.
Proceedings of the 10th International Conference on Model-Driven Engineering and Software Development, 2022


2021
Safe and secure software updates on high-performance mixed-criticality systems: The UP2DATE approach.
Microprocess. Microsystems, November, 2021

Time Measurement and Control Blocks for Bare-Metal C++ Applications.
ACM Trans. Embed. Comput. Syst., 2021

A modeling methodology for collaborative evaluation of future automotive innovations.
Softw. Syst. Model., 2021

Legacy software migration based on timing contract aware real-time execution environments.
J. Syst. Softw., 2021

Multi-core Devices for Safety-critical Systems: A Survey.
ACM Comput. Surv., 2021

The UP2DATE Baseline Research Platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Functional test environment for time-triggered control systems in complex MPSoCs.
Microprocess. Microsystems, 2020

A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCs.
Int. J. Parallel Program., 2020

Work-in-Progress: Modeling of real-time communication for industrial distributed automation systems.
Proceedings of the 16th IEEE International Conference on Factory Communication Systems, 2020

Static/dynamic real-time legacy software migration: a comparative analysis.
Proceedings of the RAPIDO 2020 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2020

Capturing Neural-Networks as Synchronous Dataflow Graphs.
Proceedings of the 23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2020

Towards Time-Sensitive Behavioral Contract Monitors for IEC 61499 Function Blocks.
Proceedings of the IEEE Conference on Industrial Cyberphysical Systems, 2020

Timing Contracts and Monitors for Safety Relevant Controller Design in IEC 61499.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020

UP2DATE: Safe and secure over-the-air software updates on high-performance mixed-criticality systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

A Compiler Comparison in the RISC-V Ecosystem.
Proceedings of the 2020 International Conference on Omni-layer Intelligent Systems, 2020

2019
Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Towards Stateflow Model Aware Debugging with LLDB.
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, 2019

Design and Analysis of an Online Update Approach for Embedded Microprocessors.
Proceedings of the Analysis, Estimations, and Applications of Embedded Systems, 2019

Time Measurement and Control Blocks for Bare-Metal C++ Applications.
Proceedings of the 2019 Forum for Specification and Design Languages, 2019

Probabilistic State-Based RT-Analysis of SDFGs on MPSoCs with Shared Memory Communication.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Multi-layer time coherency in the development of ADAS/AD systems: design approach and tooling.
Proceedings of the Workshop on Design Automation for CPS and IoT, 2019

Towards Distributed Runtime Monitoring with C++ Contracts.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

Experimental Evaluation of Scenario Aware Synchronous Data Flow based Power Management.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

SAFEPOWER: Application of Power Management Techniques in SoCs for Safety-Relevant Systems.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

2018
An Integration Flow for Mixed-Critical Embedded Systems on a Flexible Time-Triggered Platform.
ACM Trans. Design Autom. Electr. Syst., 2018

Towards power management verification of time-triggered systems using virtual platforms.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Real-Time Capable Retargeting of Xilinx MicroBlaze Binaries using QEMU: A Feasibility Study.
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018

Using IEC 61499 to Implement a Self-Organising Plug and Produce System.
Proceedings of MODELS 2018 Workshops: ModComp, 2018

Functional Test Environment for Time-Triggered Control Systems in Complex MPSoCs Using GALI.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

A Hypervisor Architecture for Low-Power Real-Time Embedded Systems.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties.
Microprocess. Microsystems, 2017

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems.
Microprocess. Microsystems, 2017

Towards virtual prototyping of synchronous real-time systems on noc-based MPSoCs.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication.
Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
A Task-Level Monitoring Framework for Multi-Processor Platforms.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

A quasi-cycle accurate timing model for binary translation based instruction set simulators.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

SAFEPOWER Project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
Application Mapping and Communication Synthesis for Object-Oriented Platform-Based Design.
PhD thesis, 2015

State-based real-time analysis of SDF applications on MPSoCs with shared communication resources.
J. Syst. Archit., 2015

Ein Verfahren zur Bestimmung eines Powermodells von Xilinx MicroBlaze MPSoCs zur Verwendung in Virtuellen Plattformen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015

Structural Contracts - Motivating Contracts to Ensure Extra-Functional Semantics.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

A workload extraction framework for software performance model generation.
Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2015

Mixed-criticality system modelling with dynamic execution mode switching.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015

Teaching Mixed-Criticality: Multi-Rotor Flight Control and Payload Processing on a Single Chip.
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, 2015

Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
A program state machine based virtual processing model in SystemC.
SIGBED Rev., 2014

An ESL timing & power estimation and simulation framework for heterogeneous socs.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Autonomous Flight Control Meets Custom Payload Processing: A Mixed-Critical Avionics Architecture Approach for Civilian UAVs.
Proceedings of the 17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2014

Towards satisfaction checking of power contracts in Uppaal.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

Data-and State-Dependent Power Characterisation and Simulation of Black-Box RTL IP Components at System Level.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014


2013
The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration.
Microprocess. Microsystems, 2013

Power contracts: A formal way towards power-closure?!
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Ansatz zur Bewertung der HW/SW-Kommunikation in asymmetrischen Multi-Prozessor-Systemen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Hierarchical real-time scheduling in the multi-core era - An overview.
Proceedings of the 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

A database for the integration of power data on system level.
Proceedings of Eurocon 2013, 2013

Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Non-invasive Power Simulation at System-Level with SystemC.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Nicht-invasive Simulation des Energieverbrauchs von Hardware-Komponenten auf Systemebene mit SystemC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

From RTL IP to functional system-level models with extra-functional properties.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Challenges of multi- and many-core architectures for electronic system-level design.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Ein generisches Treiber-Framework zur HW/SW-Kommunikation mittels OSSS-RMI.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2011

Impact simulation of changes to development processes: An ESL case study.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

2010
Distributed Resource-Aware Scheduling for Multi-core Architectures with SystemC.
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010

Towards an ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

Mapping of Concurrent Object-Oriented Models to Extended Real-Time Task Networks.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

SystemC-AMS SDF model synthesis for exploration of heterogeneous architectures.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Towards a synthesis semantics for systemC channels.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

PolyDyn - Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2008
Modelling Program-State Machines in SystemC.
Proceedings of the Forum on specification and Design Languages, 2008

SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Eine Fallstudie zur dynamischen Rekonfiguration von Hardware: "Pain or Gain?".
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

2006
Modelling and Synthesis of Communication Using OSSS-Channels.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

OSSS-Channels: Modelling and Synthesis of Communication.
Proceedings of the Forum on specification and Design Languages, 2006

Overview of the ICODES Project.
Proceedings of the Forum on specification and Design Languages, 2006

2005
Kommunikationsgetriebene Hardware-/Software Partitionierung eines Netzwerkprotokoll-Stacks auf einer SoC Plattform.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005


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