Vatistas Kostalabros

According to our database, Vatistas Kostalabros authored at least 4 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator.

Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2022

A Security Model for Randomization-based Protected Caches.

Jordi Ribes-González, Oriol Farràs, Carles Hernández, Vatistas Kostalabros, Miquel Moretó

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

2021

HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem.

Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020

An Academic RISC-V Silicon Implementation Based on Open-Source Components.

Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco Antonio Ramírez, Carlos Rojas Morales, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas Valdivieso, Luis Villa

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020