Roger Figueras

According to our database, Roger Figueras authored at least 15 papers between 2011 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2026

REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton.

Noelia Oliete-Escuín, Arnau Bigas, Narcís Rodas, Albert Aguilera, Sajjad Ahmad, Jonathan Balkind, Xavier Carril, Max Doblas, Iván Díaz, Roger Figueras, Alireza Foroodnia, César Fuguet, R. Ignacio Genovese, Raúl Gilabert, Abbas Haghi, Alexander Kropotov, Neiel Leyva, Oscar Lostes-Cazorla, Lorién López-Villellas, Davy Million, Alireza Monemi, Sérik Pérez, Juan Antonio Rodríguez, Víctor Soria Pardos, Behzad Salami, Francesc Moll, Oscar Palomar, Miquel Moretó, Lluc Alvarez

CoRR, May, 2026

2025

Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication.

Mohammadreza Esmali Nojehdeh, Hossein Mokhtarnia, Julian Pavon Rivera, Narcis Rodas Quiroga, Roger Figueras Bagué, Enrico Reggiani, Miquel Moretó, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé

CoRR, April, 2025

Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication.

Mohammadreza Esmali Nojehdeh, Hossein Mokhtarnia, Julian Pavon, Narcís Rodas, Roger Figueras Bagué, Enrico Reggiani, Miquel Moretó, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé

Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

2024

QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms.

Julian Pavon, Iván Vargas Valdivieso, Carlos Rojas, César Hernández, Mehmet Aslan, Roger Figueras, Yichao Yuan, Joël Lindegger, Mohammed Alser, Francesc Moll, Santiago Marco-Sola, Oguz Ergin, Nishil Talati, Onur Mutlu, Osman S. Unsal, Mateo Valero, Adrián Cristal

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications.

Francesco Minervini, Oscar Palomar, Osman S. Unsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González, Jonnatan Mendoza, Iván Vargas, César Hernández, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrián Cristal

ACM Trans. Archit. Code Optim., June, 2023

WFAsic: A High-Performance ASIC Accelerator for DNA Sequence Alignment on a RISC-V SoC.

Abbas Haghi, Lluc Alvarez, Jordi Fornt, Juan Miguel De Haro Ruiz, Roger Figueras, Max Doblas, Santiago Marco-Sola, Miquel Moretó

Proceedings of the 52nd International Conference on Parallel Processing, 2023

VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing.

Julián Pavón, Iván Vargas Valdivieso, Joan Marimon, Roger Figueras, Francesc Moll, Osman S. Unsal, Mateo Valero, Adrián Cristal

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology.

Max Doblas, Gerard Candón, Xavier Carril, Marc Domínguez, Enric Erra, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Josep Oltra, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Hugo Safadi, Víctor Soria, Alejandro Suanes, Iván Vargas, Fernando Arreza, Roger Figueras, Pau Fontova-Musté, Joan Marimon, Ricardo Martínez, Sergio Moreno, Jordi Sacristán, Oscar Alonso, Xavier Aragonès, Adrián Cristal, Ángel Diéguez, Manuel López, Diego Mateo, Francesc Moll, Miquel Moretó, Oscar Palomar, Marco A. Ramírez, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luis Villa

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022

Adaptable Register File Organization for Vector Processors.

Cristóbal Ramírez Lazo, Enrico Reggiani, Carlos Rojas Morales, Roger Figueras Bagué, Luis A. Villa Vargas, Marco Antonio Ramírez Salinas, Mateo Valero Cortés, Osman Sabri Unsal, Adrián Cristal

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology.

Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio, Jordi Sacristán, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luis Villa

Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge.

Enrico Reggiani, Cristóbal Ramírez Lazo, Roger Figueras Bagué, Adrián Cristal, Mauro Olivieri, Osman Sabri Unsal

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2020

An Academic RISC-V Silicon Implementation Based on Open-Source Components.

Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco Antonio Ramírez, Carlos Rojas, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas Valdivieso, Luis Villa

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2018

A 128× 128-pix 4-kfps 14-bit Digital-Pixel PbSe-CMOS Uncooled MWIR Imager.

Roger Figueras, Josep Maria Margarit, German Vergara, Victor Villamayor, Raúl Gutiérrez-Álvarez, Carlos Fernández-Montojo, Lluís Terés, Francisco Serra-Graells

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers.

Michele Dei, Roger Figueras, Josep Maria Margarit, Lluís Terés, Francisco Serra-Graells

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2011

A 70-mu m Pitch 8-mu W Self-Biased Charge-Integration Active Pixel for Digital Mammography.

Roger Figueras, Justo Sabadell, Lluís Terés, Francisco Serra-Graells

IEEE Trans. Biomed. Circuits Syst., 2011