Vinay Joshi
Orcid: 0000-0001-6031-1669
According to our database1,
Vinay Joshi
authored at least 14 papers
between 2016 and 2025.
Collaborative distances:
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Bibliography
2025
TaDA: Training-free recipe for Decoding with Adaptive KV Cache Compression and Mean-centering.
CoRR, June, 2025
2024
CiMNet: Towards Joint Optimization for DNN Architecture and Configuration for Compute-In-Memory Hardware.
CoRR, 2024
Towards Robust mmWave-based Human Activity Recognition using Large Simulated Dataset for Model Pretraining.
Proceedings of the IEEE International Conference on Big Data, 2024
2022
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.
CoRR, 2022
2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
CoRR, 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2016
Proceedings of the 12th International Conference on Signal-Image Technology & Internet-Based Systems, 2016