Martino Dazzi

Orcid: 0000-0002-4184-2170

According to our database1, Martino Dazzi authored at least 19 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2024

2023
Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors.
IEEE Wirel. Commun., August, 2023

ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning.
IEEE Trans. Computers, July, 2023

2022
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.
CoRR, 2022

2021
Accelerating Inference of CNNs with In-Memory Computing.
PhD thesis, 2021

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Efficient Pipelined Execution of CNNs Based on In-Memory Computing and Graph Homomorphism Verification.
IEEE Trans. Computers, 2021

Accelerating Inference of Convolutional Neural Networks Using In-memory Computing.
Frontiers Comput. Neurosci., 2021

A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS.
CoRR, 2021

Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH).
Proceedings of the CF '21: Computing Frontiers Conference, 2021

2020
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors.
CoRR, 2020

Compiling Neural Networks for a Computational Memory Accelerator.
CoRR, 2020

2019
Deep learning acceleration based on in-memory computing.
IBM J. Res. Dev., 2019

5 Parallel Prism: A topology for pipelined implementations of convolutional neural networks using computational memory.
CoRR, 2019

Accurate deep neural network inference using computational phase-change memory.
CoRR, 2019

Computational memory-based inference and training of deep neural networks.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces.
Proceedings of the 42nd International Convention on Information and Communication Technology, 2019

A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018


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