Vladimir Petrovic

According to our database1, Vladimir Petrovic authored at least 22 papers between 2005 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
Design of an On-chip System for the SET Pulse Width Measurement.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Enhanced architectures for soft error detection and correction in combinational and sequential circuits.
Microelectron. Reliab., 2016

A comprehensive approach to fault tolerance: Device, circuit, and system techniques.
Proceedings of the 17th Latin-American Test Symposium, 2016

SET response of a SEL protection switch for 130 and 250 nm CMOS technologies.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Implementation of a real time unit for satellite applications.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Implementation of DBFN processor for Synthetic Aperture Radar application.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Focused pooling for image fusion evaluation.
Inf. Fusion, 2015

Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch.
J. Electron. Test., 2015

Design Flow for Radhard TMR Flip-Flops.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Simulation-Based Analysis of the Single Event Transient Response of a Single Event Latchup Protection Switch.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
Fault-tolerant TMR and DMR circuits with latchup protection switches.
Microelectron. Reliab., 2014

Reconfigurable Low Power Architecture for Fault Tolerant Pseudo-Random number Generation.
J. Circuits Syst. Comput., 2014

Improved circuitry for soft error correction in combinational logic in pipelined designs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Fault tolerant implementation of a SpaceWire interface.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Focused pooling for objective quality estimation.
Proceedings of the IEEE International Conference on Image Processing, 2013

Redundant circuits with latchup protection.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Human-Robot Analogy - How Physiology Shapes Human and Robot Motion.
Proceedings of the Twelfth European Conference on the Synthesis and Simulation of Living Systems: Advances in Artificial Life, 2013

Fault-Tolerant Reconfigurable Low-Power pseudoRandom number Generator.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
A multi-banked shared-l1 cache architecture for tightly coupled processor clusters.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Design methodology for fault tolerant ASICs.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Middleware switch ASIC implementation.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2005
Mobile Phone Antenna Performance and Power Absorption in Terms of Handset Size and Distance from User's Head.
Wirel. Pers. Commun., 2005


  Loading...