Weihai Bu

According to our database, Weihai Bu authored at least 5 papers between 2001 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2026

Variation-aware optimization of salicide-enhanced tunnel FET technology based on 300 mm foundry platform.

Kaifeng Wang, Yiqing Li, Ye Ren, Yongqin Wu, Weihai Bu, Qianqian Huang, Ru Huang

Sci. China Inf. Sci., 2026

2024

A 3.75Mb Embedded RRAM IP on 40nm High-Voltage CMOS Technology.

Yuan He, Chengxiang Ma, Xiangchao Ma, Yilong Huang, Qianze Zheng, Yue Xi, Qiumeng Wei, Jianing Li, Xiaodong He, Yongqin Wu, Weihai Bu, Kai Zheng, Jin Kang, Jianshi Tang, Bin Gao, Dong Wu, He Qian, Huaqiang Wu

Proceedings of the IEEE International Memory Workshop, 2024

2023

First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology.

Kaifeng Wang, Yongqin Wu, Ye Ren, Renjie Wei, Zerui Chen, Jianfeng Hang, Zhixuan Wang, Fangxing Zhang, Lining Zhang, Chunyu Peng, Xiulong Wu, Le Ye, Kai Zheng, Jin Kang, Xusheng Wu, Weihai Bu, Ru Huang, Qianqian Huang

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

A Novel TFET-MOSFET Hybrid SRAM for Ultra-Low-Power Applications.

Renjie Wei, Kaifeng Wang, Zhixuan Wang, Libo Yang, Fangxing Zhang, Yongqin Wu, Ye Ren, Le Ye, Lining Zhang, Weihai Bu, Ru Huang, Qianqian Huang

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2001

Quasi-two-dimensional subthreshold current model of deep submicrometer SOI drive-in gate controlled hybrid transistors with lateral non-uniform doping profile.

Ru Huang, Weihai Bu, Xing Zhang, Yangyuan Wang

Sci. China Ser. F Inf. Sci., 2001