Yangyuan Wang
According to our database1,
Yangyuan Wang
authored at least 43 papers
between 2001 and 2022.
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Bibliography
2022
Physical investigation of subthreshold swing degradation behavior in negative capacitance FET.
Sci. China Inf. Sci., 2022
Experimental investigation of the gate voltage range of negative differential capacitance in ferroelectric transistors.
Sci. China Inf. Sci., 2022
2021
The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.
IEEE J. Solid State Circuits, 2021
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network.
IEEE J. Solid State Circuits, 2021
12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
New-Generation Design-Technology Co-Optimization (DTCO): Machine-Learning Assisted Modeling Framework.
CoRR, 2019
Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling, experimental evidence, and impact on circuits.
Microelectron. Reliab., 2018
Evaluation of SRAM V<sub>min</sub> shift induced by random telegraph noise (RTN): physical understanding and prediction method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Investigation on the amplitude coupling effect of random telegraph noise (RTN) in nanoscale FinFETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2017
Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
2016
Physical understanding and optimization of resistive switching characteristics in oxide-RRAM.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A comb-gate silicon tunneling field effect transistor with improved on-state current.
Sci. China Inf. Sci., 2013
Impacts of short-channel effects on the random threshold voltage variation in nanoscale transistors.
Sci. China Inf. Sci., 2013
2012
High temperature induced failure in Ti/Al/Ni/Au Ohmic contacts on AlGaN/GaN heterostructure.
Microelectron. Reliab., 2012
IEEE Embed. Syst. Lett., 2012
A low power and small area all digital delay-locked loop based on ring oscillator architecture.
Sci. China Inf. Sci., 2012
2011
Microelectron. Reliab., 2011
The driving force for development of IC and system in future: Reducing the power consumption and improving the ratio of performance to power consumption.
Sci. China Inf. Sci., 2011
Sci. China Inf. Sci., 2011
Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Deteriorated radiation effects impact on the characteristics of MOS transistors with multi-finger configuration.
Microelectron. Reliab., 2010
IEEE J. Solid State Circuits, 2010
IEEE J. Solid State Circuits, 2010
Sci. China Inf. Sci., 2010
2009
2008
Sci. China Ser. F Inf. Sci., 2008
2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
2006
Frequency-Independent Asymmetric Double-$pi $Equivalent Circuit for On-Chip Spiral Inductors: Physics-Based Modeling and Parameter Extraction.
IEEE J. Solid State Circuits, 2006
A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
A Complete Carrier-Based Non-Charge-Sheet Analytic Theory for Nano-Scale Undoped Surrounding-Gate MOSFETs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
2003
Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET's (n-DTMOSFET) measured by gated-diode configuration.
Microelectron. Reliab., 2003
2002
Application of forward gated-diode R-G current method in extracting F-N stress-induced interface traps in SOI NMOSFETs.
Microelectron. Reliab., 2002
2001
Extraction of the lateral distribution of interface traps in MOSFETs by a novel combined gated-diode technique.
Microelectron. Reliab., 2001
Quasi-two-dimensional subthreshold current model of deep submicrometer SOI drive-in gate controlled hybrid transistors with lateral non-uniform doping profile.
Sci. China Ser. F Inf. Sci., 2001