Yasuhisa Shimazaki
According to our database1,
Yasuhisa Shimazaki
authored at least 23 papers
between 2004 and 2023.
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Bibliography
2023
A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2020
A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D.
IEEE J. Solid State Circuits, 2020
2019
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2013
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.
IEEE J. Solid State Circuits, 2013
2012
A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012
2010
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.
IEEE J. Solid State Circuits, 2010
2009
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.
IEEE J. Solid State Circuits, 2007
2006
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique.
IEEE J. Solid State Circuits, 2006
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Hierarchical power distribution and power management scheme for a single chip mobile processor.
Proceedings of the 43rd Design Automation Conference, 2006
2005
A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor.
IEEE J. Solid State Circuits, 2005
A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones.
IEICE Trans. Electron., 2005
2004