Yu Gong
Orcid: 0000-0002-2736-4635
According to our database1,
Yu Gong
authored at least 41 papers
between 2013 and 2025.
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Bibliography
2025
A Dual-Swing-Sample-and-Couple Sense Amplifier With Large Sensing Margin for STT-MRAM.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
PreDAC: An Efficient Framework of Pre-Refining Enhanced Design Space Exploration for Approximate Computing.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
2024
VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024
Truly Random Number Generation by Using in-Plane Magnetic Tunnel Junction with Weak Anisotropy.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2024
A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration.
Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024
2023
Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition.
IEEE Des. Test, June, 2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
2022
More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2021
Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Low-Power Keyword Recognition Feature Extraction Circuit based on SRMFCC and Shared Multiplier for High Noise Background.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
An Always-on Ultra-Low Power Speaker Verification Accelerator based on Binary Weighted Neural Network with System Co-optimization.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor.
IEEE Trans. Circuits Syst., 2020
IEEE Access, 2020
QCNN Inspired Reconfigurable Keyword Spotting Processor With Hybrid Data-Weight Reuse Methods.
IEEE Access, 2020
Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2019
An energy-efficient voice activity detector using deep neural networks and approximate computing.
Microelectron. J., 2019
ARA: Cross-Layer approximate computing framework based reconfigurable architecture for CNNs.
Microelectron. J., 2019
An Ultra-Low Power Always-On Keyword Spotting Accelerator Using Quantized Convolutional Neural Network and Voltage-Domain Analog Switching Network-Based Approximate Computing.
IEEE Access, 2019
EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing.
IEEE Access, 2019
Proceedings of the International Conference on Field-Programmable Technology, 2019
2018
EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier.
IEICE Electron. Express, 2018
EERA-ASR: An Energy-Efficient Reconfigurable Architecture for Automatic Speech Recognition With Hybrid DNN and Approximate Computing.
IEEE Access, 2018
An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
2017
E-ERA: An energy-efficient reconfigurable architecture for RNNs using dynamically adaptive approximate computing.
IEICE Electron. Express, 2017
Proceedings of the 2017 IEEE Symposium Series on Computational Intelligence, 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Proceedings of the 2017 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2017
2016
A Novel Design of Pipeline MDC-FFT Processor Based on Various Memory Access Mechanism.
Proceedings of the International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2016
2015
Performance-Conscious Reconfiguration Structure for Large-Scale Coarse-Grained Reconfigurable System.
Proceedings of the 2015 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2015
A novel routing structure of coarse-grained reconfigurable architecture for radar application.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
Proceedings of the 2nd IAPR Asian Conference on Pattern Recognition, 2013