Yu-Tsao Hsing

According to our database, Yu-Tsao Hsing authored at least 8 papers between 2004 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

3D-IC BISR for stacked memories using cross-die spares.

Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2010

SOC Test Architecture and Method for 3-D ICs.

Chih-Yen Lo, Yu-Tsao Hsing, Li-Ming Denq, Cheng-Wen Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Economic Analysis of the HOY Wireless Test Methodology.

Yu-Tsao Hsing, Li-Ming Denq, Chao-Hsun Chen, Cheng-Wen Wu

IEEE Des. Test Comput., 2010

2009

Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories.

Li-Ming Denq, Yu-Tsao Hsing, Cheng-Wen Wu

IEEE Des. Test Comput., 2009

An Adaptive-Rate Error Correction Scheme for NAND Flash Memory.

Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing, Cheng-Wen Wu

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2007

SDRAM Delay Fault Modeling and Performance Testing.

Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

2006

Fault-Pattern Oriented Defect Diagnosis for Flash Memory.

Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu

Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

2004

Failure Factor Based Yield Enhancement for SRAM Designs.

Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004