Youssef Travaly

According to our database1, Youssef Travaly authored at least 11 papers between 2006 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2011
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

In-tier diagnosis of power domains in 3D TSV ICs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures.
Microelectron. Reliab., 2010


Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

A novel concept for ultra-low capacitance via-last TSV.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV).
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping.
Proceedings of the IEEE International Conference on 3D System Integration, 2009


2006
Impact of interconnect resistance increase on system performance of low power and high performance designs.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006


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