Eric Beyne

According to our database1, Eric Beyne authored at least 76 papers between 1995 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2022
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy.
IEEE Trans. Instrum. Meas., 2021

Design and Technology Solutions for 3D Integrated High Performance Systems.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited).
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

2019
Process Complexity and Cost Considerations of Multi-Layer Die Stacks.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Protective Layer for Collective Die to Wafer Hybrid Bonding.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly.
Microelectron. Reliab., 2018

A study on substrate noise coupling among TSVs in 3D chip stack.
IEICE Electron. Express, 2018

TSV process-induced MOS reliability degradation.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Stress mitigation of 3D-stacking/packaging induced stresses.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects.
Microelectron. Reliab., 2017

Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices.
Microelectron. Reliab., 2017

2016
Reliability Challenges Related to TSV Integration and 3-D Stacking.
IEEE Des. Test, 2016

The 3-D Interconnect Technology Landscape.
IEEE Des. Test, 2016

Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Extreme wafer thinning optimization for via-last applications.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Die to wafer 3D stacking for below 10um pitch microbumps.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Microstructure simulation of grain growth in Cu through silicon vias using phase-field modeling.
Microelectron. Reliab., 2015


Impact of oxide liner properties on TSV Cu pumping and TSV stress.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Thermal experimental and modeling analysis of high power 3D packages.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Through silicon via to FinFET noise coupling in 3-D integrated circuits.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Processing active devices on Si interposer and impact on cost.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

3D system integration research at IMEC.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling.
Microelectron. Reliab., 2014

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias.
Microelectron. Reliab., 2014

Fast convolution based thermal model for 3D-ICs: Methodology, accuracy analysis and package impact.
Microelectron. J., 2014

System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.
IEEE Embed. Syst. Lett., 2014

Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Analysis of 3D interconnect performance: Effect of the Si substrate resistivity.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Design issues in heterogeneous 3D/2.5D integration.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Si interposer build-up options and impact on 3D system cost.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
Cu pumping in TSVs: Effect of pre-CMP thermal budget.
Microelectron. Reliab., 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations.
Proceedings of the Design, Automation and Test in Europe, 2011

3D heterogeneous system integration: application driver for 3D technology development.
Proceedings of the 48th Design Automation Conference, 2011

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

3D stacking using ultra thin dies.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Analysis of microbump induced stress effects in 3D stacked IC technologies.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

3D stacking using Cu-Cu direct bonding.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

In-line metrology and inspection for process control during 3D stacking of IC's.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices - Technology directions.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

In-tier diagnosis of power domains in 3D TSV ICs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Cost effectiveness of 3D integration options.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

A novel concept for ultra-low capacitance via-last TSV.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot.
Proc. IEEE, 2009

Impact of 3D design choices on manufacturing cost.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV).
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2007
Thermal cycling reliability of SnAgCu and SnPb solder joints: A comparison for several IC-packages.
Microelectron. Reliab., 2007

Tutorial T7A: Advanced IC Packaging.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Wafer-level package interconnect options.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Technologies for highly miniaturized autonomous sensor networks.
Microelectron. J., 2006

Constant impedance scaling paradigm for interconnect synthesis.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Efficient Link Architecture for On-Chip Serial links and Networks.
Proceedings of the International Symposium on System-on-Chip, 2006

Constant Impedance Scaling Paradigm for Scaling LC transmission lines.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Active Electrode Arrays by Chip Embedding in a Flexible Silicone Carrier.
Proceedings of the 28th International Conference of the IEEE Engineering in Medicine and Biology Society, 2006

Analysis and modeling of power grid transmission lines.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Package level interconnect options.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

2004
Characterization and FE analysis on the shear test of electronic materials.
Microelectron. Reliab., 2004

2003
Modified micro-macro thermo-mechanical modelling of ceramic ball grid array packages.
Microelectron. Reliab., 2003

Advantage of In-situ over Ex-situ techniques as reliability tool: Aging kinetics of Imec's MCM-D discrete passives devices.
Microelectron. Reliab., 2003

Direct gold and copper wires bonding on copper.
Microelectron. Reliab., 2003

The influence of packaging materials on RF performance.
Microelectron. Reliab., 2003

2000
Chip-package codesign of a low-power 5-GHz RF front end.
Proc. IEEE, 2000

1996
Design of Test Modules for the Analysis of MCM Interconnects.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Signal propagation in high-speed MCM circuits.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995


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