Alberto A. Del Barrio

Orcid: 0000-0002-6769-1200

Affiliations:
  • Complutense University of Madrid, Spain


According to our database1, Alberto A. Del Barrio authored at least 61 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
HUB Meets Posit: Arithmetic Units Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023
Generating Posit-Based Accelerators With High-Level Synthesis.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

Design and simulation of memristor-based neural networks.
CoRR, 2023

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing.
CoRR, 2023

PLAUs: Posit Logarithmic Approximate Units to Implement Low-Cost Operations with Real Numbers.
Proceedings of the Next Generation Arithmetic - 4th International Conference, 2023

PERCIVAL: Deploying Posits and Quire Arithmetic into the CVA6 RISC-V Core.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

A Suite of Division Algorithms for Posit Arithmetic.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

2022
PLAM: A Posit Logarithm-Approximate Multiplier.
IEEE Trans. Emerg. Top. Comput., 2022

PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability.
IEEE Trans. Emerg. Top. Comput., 2022

The Effects of Approximate Multiplication on Convolutional Neural Networks.
IEEE Trans. Emerg. Top. Comput., 2022

CTMQ: Cyclic Training of Convolutional Neural Networks with Multiple Quantization Steps.
CoRR, 2022

Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

Comparing Different Decodings for Posit Arithmetic.
Proceedings of the Next Generation Arithmetic - Third International Conference, 2022

The Effects of Numerical Precision In Scientific Applications.
Proceedings of the Annual Modeling and Simulation Conference, 2022

2021
First experiences of teaching quantum computing.
J. Supercomput., 2021

A Cluster of FPAAs to Recognize Images Using Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

PLAM: a Posit Logarithm-Approximate Multiplier for Power Efficient Posit-based DNNs.
CoRR, 2021

A Cost-Efficient Approximate Dynamic Ranged Multiplication and Approximation-Aware Training on Convolutional Neural Networks.
IEEE Access, 2021

Energy-Efficient MAC Units for Fused Posit Arithmetic.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020
HEVC optimization based on human perception for real-time environments.
Multim. Tools Appl., 2020

Deep PeNSieve: A deep learning framework based on the posit number system.
Digit. Signal Process., 2020

LiveChess2FEN: a Framework for Classifying Chess Pieces based on CNNs.
CoRR, 2020

Securing high-resolution train videos encoded with HEVC and inter prediction mode.
Comput. Ind., 2020

CNN Inference acceleration using low-power devices for human monitoring and security scenarios.
Comput. Electr. Eng., 2020

Efficient embedding and retrieval of information for high-resolution videos coded with HEVC.
Comput. Electr. Eng., 2020

Customized Posit Adders and Multipliers using the FloPoCo Core Generator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks.
IEEE Trans. Computers, 2019

Template-Based Posit Multiplication for Training and Inferring in Neural Networks.
CoRR, 2019

SMURF: Systematic Methodology for Unveiling Relevant Factors in Retrospective Data on Chronic Disease Treatments.
IEEE Access, 2019

A study on the parallelization of moeas to predict the patient's response to the onabotulinumtoxina treatment.
Proceedings of the 2019 Summer Simulation Conference, 2019

Simulating and executing circuits employing the quantum computing paradigm.
Proceedings of the 2019 Summer Simulation Conference, 2019

Design of Power-Efficient FPGA Convolutional Cores with Approximate Log Multiplier.
Proceedings of the 27th European Symposium on Artificial Neural Networks, 2019

A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018
Fast and effective CU size decision based on spatial and temporal homogeneity detection.
Multim. Tools Appl., 2018

Complexity reduction in the HEVC/H265 standard based on smooth region classification.
Digit. Signal Process., 2018

Data hiding algorithm for HEVC using intra-coded frames.
Proceedings of the 50th Computer Simulation Conference, 2018

An ultra low-cost cluster based on low-end FPGAs.
Proceedings of the 50th Computer Simulation Conference, 2018

Intra-Steganography: Hiding Data in High-Resolution Videos.
Proceedings of the 22nd IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2018

Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Support System to Improve Reading Activity in Parkinson's Disease and Essential Tremor Patients.
Sensors, 2017

A DCT and neural network based system to obtain the characteristics of biological images.
Proceedings of the Summer Simulation Multi-Conference, 2017

Simulation and implementation of a low-cost platform to improve the quality of biological images.
Proceedings of the Summer Simulation Multi-Conference, 2017

A slack-based approach to efficiently deploy radix 8 booth multipliers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier.
IEEE Trans. Computers, 2016

A distributed HW-SW platform for fireworks.
Proceedings of the Summer Computer Simulation Conference, 2016

4K-based intra and interprediction techniques for HEVC.
Proceedings of the Real-Time Image and Video Processing 2016, 2016

2014
Ultra-low-power adder stage design for exascale floating point units.
ACM Trans. Embed. Comput. Syst., 2014

Improving circuit performance with multispeculative additive trees in high-level synthesis.
Microelectron. J., 2014

Generic Markov model of the contention access period of IEEE 802.15.4 MAC layer.
Digit. Signal Process., 2014

2013
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths.
Integr., 2013

Exploring the energy efficiency of Multispeculative Adders.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Multispeculative additive trees in high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Multispeculative Addition Applied to Datapath Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Power optimization in heterogenous datapaths.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Using Speculative Functional Units in high level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Subword Switching Activity Minimization to Optimize Dynamic Power Consumption.
IEEE Des. Test Comput., 2009

2008
Applying speculation techniques to implement functional units.
Proceedings of the 26th International Conference on Computer Design, 2008

Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008


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