Jose Manuel Mendias

According to our database1, Jose Manuel Mendias authored at least 67 papers between 1996 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2015
Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2015

2014
Improving circuit performance with multispeculative additive trees in high-level synthesis.
Microelectronics Journal, 2014

2013
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths.
Integr., 2013

Multispeculative additive trees in high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Multispeculative Addition Applied to Datapath Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

2011
A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Power optimization in heterogenous datapaths.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Software metadata: Systematic characterization of the memory behaviour of dynamic applications.
Journal of Systems and Software, 2010

Using Speculative Functional Units in high level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Direct memory access usage optimization in network applications for reduced memory latency and energy consumption.
J. Embedded Computing, 2009

Performance-driven scheduling of behavioural specifications.
Integr., 2009

Subword Switching Activity Minimization to Optimize Dynamic Power Consumption.
IEEE Design & Test of Computers, 2009

2008
Applying speculation techniques to implement functional units.
Proceedings of the 26th International Conference on Computer Design, 2008

Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
HW-SW emulation framework for temperature-aware design in MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2007

Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Multi-processor operating system emulation framework with thermal feedback for systems-on-chip.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Area optimization of multi-cycle operators in high-level synthesis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Systematic dynamic memory management design methodology for reduced memory footprint.
ACM Trans. Design Autom. Electr. Syst., 2006

Bitwise scheduling to balance the computational cost of behavioral specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems.
Integr., 2006

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Systematic design flow for dynamic data management in visual texture decoder of MPEG-4.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Pre-synthesis optimization of multiplications to improve circuit performance.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications.
VLSI Signal Processing, 2005

Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications.
Proceedings of the Wired/Wireless Internet Communications, Third International Conference, 2005

Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2005

Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

A novel approach for network on chip emulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Performance-driven read-after-write dependencies softening in high-level synthesis.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis.
Proceedings of the 2005 Design, 2005

A Complete Network-On-Chip Emulation Framework.
Proceedings of the 2005 Design, 2005

Arrival time aware scheduling to minimize clock cycle length.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Memory-access-aware data structure transformations for embedded software with dynamic data accesses.
IEEE Trans. VLSI Syst., 2004

Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology.
Proceedings of the Wired/Wireless Internet Communications, Second International Conference, 2004

Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2004

Behavioural Scheduling to Balance the Bit-Level Computational Effort.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

Reducing memory accesses with a system-level design methodology in customized dynamic memory management.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

Behavioural Bitwise Scheduling Based on Computational Effort Balancing.
Proceedings of the 2004 Design, 2004

Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications.
Proceedings of the 2004 Design, 2004

An integrated hardware/software approach for run-time scratchpad management.
Proceedings of the 41th Design Automation Conference, 2004

Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded Systems.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources.
Journal of Systems Architecture, 2003

Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.
Proceedings of the Integrated Circuit and System Design, 2003

Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level.
Proceedings of the Integrated Circuit and System Design, 2003

High-Level Allocation to Minimize Internal Hardware Wastage.
Proceedings of the 2003 Design, 2003

2002
A global approach to improve conditional hardware reuse in high-level synthesis.
Journal of Systems Architecture, 2002

A study about the efficiency of formal high-level synthesis applied to verification.
Integr., 2002

Bit-level scheduling of heterogeneous behavioural specifications.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Transformation of Equational Specification by Means of Genetic Programming.
Proceedings of the Genetic Programming, 5th European Conference, 2002

Source Code Transformation to Improve Conditional Hardware Reuse.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Bit-Level Allocation of Multiple-Precision Specifications.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Optimization of Equational Specifications Using Genetic Techniques.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Maximizing Conditonal Reuse by Pre-Synthesis Transformations.
Proceedings of the 2002 Design, 2002

Multiple-Precision Circuits Allocation Independent of Data-Objects Length.
Proceedings of the 2002 Design, 2002

High-level synthesis of multiple-precision circuitsindependent of data-objects length.
Proceedings of the 39th Design Automation Conference, 2002

2000
Execution Condition Analysis in High Level Synthesis: A Unified Approach.
Proceedings of the 13th International Symposium on System Synthesis, 2000

1999
A Unified Algorithm for Mutual Exclusiveness Identification.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
Correct High-Level Synthesis: a Formal Perspective.
Proceedings of the 1998 Design, 1998

1997
Formal Techniques for Hardware Allocation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
Algebraic Support for Transformational Hardware Allocation.
Proceedings of the 1996 European Design and Test Conference, 1996


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