Alessandro Cabrini

Orcid: 0000-0003-1862-2409

According to our database1, Alessandro Cabrini authored at least 52 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Designing Circuits for AiMC Based on Non-Volatile Memories: A Tutorial Brief on Trade-Off and Strategies for ADCs and DACs Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023
Ultra-Low-Power Low-Input-Voltage Charge Pump for Micro-Energy Harvesting Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

2022
Ultra Low-Power, Area-Efficient Multiplier Based on Shift-and-Add Architecture.
Proceedings of the 29th International Conference on Mixed Design of Integrated Circuits and System, 2022

An Extended Temperature Range ePCM Memory in 90-nm BCD for Smart Power Applications.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2020
Enhanced Compensation for Voltage Regulators Based on Three-Stage CMOS Operational Amplifiers for Large Capacitive Loads.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Current Tracking Technique Enabling 1-Bit/Cell Storage in Ge-Rich Phase Change Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Selector-Memory Device Voltage Compatibility Considerations in 1S1R Crosspoint Arrays.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

Enhanced Multiple-Output Programmable Current Pulse Generator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Drift induced rigid current shift in Ge-Rich GST Phase Change Memories in Low Resistance State.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications.
IEEE J. Solid State Circuits, 2018

A Variability-Aware Analysis and Design Guideline for Write and Read Operations in Crosspoint STT-MRAM Arrays.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

2017
A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
Integrated charge pumps: a generalised method for power efficiency optimisation.
IET Circuits Devices Syst., 2016

Magnetic field analysis for the optimization of a GMR isolator for data transmission in power applications.
Proceedings of the IECON 2016, 2016

Bandwidth optimization of CMOS two-stage operational amplifiers under power consumption and area constraints.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Enhanced voltage buffer compensation technique for two-stage CMOS operational amplifiers.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Optimized temperature profile based pulse generator for innovative Phase Change Memory.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Current pulse generator for multilevel cell programming of innovative PCM.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014
Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions.
IEEE Trans. Inf. Forensics Secur., 2014

Optimal programming with voltage-controlled temperature profile to reduce SET state distribution dispersion in PCM.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A theoretical charge transfer scheme for efficiency optimization of integrated charge pumps.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Drift-driven investigation of phase distribution in phase-change memories.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Leakage-resilient memory-based physical unclonable function using phase change material.
Proceedings of the International Carnahan Conference on Security Technology, 2014

2013
High-swing buffer for programmable resistive memories.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

Automatic trimming procedure to enhance the accuracy of on-chip analog pulse generators.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012
High-drive capability buffer for highly variable resistive loads.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Current reference scheme for multilevel phase-change memory sensing.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2009
A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage.
IEEE J. Solid State Circuits, 2009

2008

Temperature dependence of the programmed states in GST-based multilevel phase-change memories.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Voltage Gain Analysis of Integrated Fibonacci-Like Charge Pumps for Low Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Cancellation of Amplifier Offset and 1/f Noise: An Improved Chopper Stabilized Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Impact of Control Signal Non-Idealties on Two-Phase Charge Pumps.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of Maximum-Efficiency Integrated Voltage Doubler.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A discussion on exponential-gain charge pump.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Impact of control signal skews on self-boosted charge pumps.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Thermal regulator for IC temperature characterization using a microprobe station.
IEEE Trans. Instrum. Meas., 2006

Power efficiency evaluation in Dickson and voltage doubler charge pump topologies.
Microelectron. J., 2006

Impact of parasitic elements on CMOS charge pumps: a numerical analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On-line calibration of offset and gain mismatch in time-interleaved ADC using a sampled-data chaotic bit-stream.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Theoretical and experimental analysis of Dickson charge pump output resistance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-Efficiency CMOS Charge Pump.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

High-Efficiency Regulated Charge Pump for Non-Volatile Memories.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
High-efficiency control structure for CMOS flash memory charge pumps.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Efficiency comparison between doubler and Dickson charge pumps.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 1.2 V sense amplifier for high-performance embeddable NOR flash memories.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 1 V, 26 μW extended temperature range band-gap reference in 130-nm CMOS technology.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

Use of non-linear Chua's circuit for on-line offset calibration of ADC.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A theoretical discussion on performance limits of CMOS charge pumps.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
High input range sense comparator for multilevel Flash memories.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
On-chip error correcting techniques for new-generation flash memories.
Proc. IEEE, 2003


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