Vikas Rana

Orcid: 0000-0001-5432-0286

According to our database1, Vikas Rana authored at least 45 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style.
IEEE Embed. Syst. Lett., December, 2023

A Study of the Electroforming Process in 1T1R Memory Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory.
CoRR, 2023

PR-PUF: A Reconfigurable Strong RRAM PUF.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

A Simplified Variability-Aware VCM Memristor Model for Efficient Circuit Simulation.
Proceedings of the 19th International Conference on Synthesis, 2023

Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Finite State Automata Design using 1T1R ReRAM Crossbar.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Exploration of Bistable Oscillatory Dynamics in a Memristor from Forschungszentrum Jülich.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

Design and Analysis of Isolated Voltage-Mode Memristor Cellular Nonlinear Network Cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Toward Simplified Physics-Based Memristor Modeling of Valence Change Mechanism Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Performance Analysis of Memristive-CNN based on a VCM Device Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Experimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022


2021
Adaptive Forward Body Bias Voltage Generator.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Negative Voltage Generator and Current DAC Based Regulator For Flash Memory.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Tuning the Memory Window of TaOx ReRAM Using the RF Sputtering Power.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Implementation of Multinary Łukasiewicz Logic Using Memristive Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

50x Endurance Improvement in TaOx RRAM by Extrinsic Doping.
Proceedings of the IEEE International Memory Workshop, 2021

System Theory Enables a Deep Exploration of ReRAM Cells' Switching Phenomena.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Intelligent patient monitoring for proactive alerting of key personnel in intensive care: A single-center study.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021

2020
Power Efficient Sense Amplifier For Emerging Non Volatile Memories.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Switched Capacitor Based Area Efficient Voltage Quadruple for High Pumping Efficiency.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

A Compact Model for the Electroforming Process of Memristive Devices.
Proceedings of the European Conference on Circuit Theory and Design, 2020

2019
Current DAC Based -40dB PSRR Configurable Output LDO in BCD Technology.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
Stress Relaxed Multiple Output High-Voltage Level Shifter.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Row decoder for embedded Phase Change Memory using low voltage transistors.
Microelectron. J., 2018

A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications.
IEEE J. Solid State Circuits, 2018

CMOS Oscillator Having Stable Frequency with Process, Temperature and Voltage Variation.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Area Efficient NMOS Based Positive and Negative Voltage Multiplier.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Switched Capacitor based High Positive and Negative Voltage Charge-pump using Sample and Hold technique.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Switched Capacitor based Area Efficient Positive and Negative Voltage Multiplier.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Single charge-pump generating high positive and negative voltages driving common load.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

A 10 MHz, 42 ppm/ °C, 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
-1.1V to +1.1V 3: 1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOI.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Lowering forming voltage and forming-free behavior of Ta2O5 ReRAM devices.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2012
Recent progress in redox-based resistive switching.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012


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