Amir H. Ashouri

Orcid: 0000-0001-8606-6497

Affiliations:
  • University of Toronto, Department of Electrical and Computer Engineering, ON, Canada
  • Polytechnic University of Milan, Italy (PhD 2016)


According to our database1, Amir H. Ashouri authored at least 16 papers between 2013 and 2023.

Collaborative distances:

Timeline

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Bibliography

2023
ACPO: AI-Enabled Compiler-Driven Program Optimization.
CoRR, 2023

2022
MLGOPerf: An ML Guided Inliner to Optimize Performance.
CoRR, 2022

Work-in-Progress: MLGOPerf: An ML Guided Inliner to Optimize Performance.
Proceedings of the International Conference on Compilers, 2022

2019
Retraining-free methods for fast on-the-fly pruning of convolutional neural networks.
Neurocomputing, 2019

A Survey on Compiler Autotuning using Machine Learning.
ACM Comput. Surv., 2019

2018
Fast On-the-fly Retraining-free Sparsification of Convolutional Neural Networks.
CoRR, 2018

SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018


Automatic Tuning of Compilers Using Machine Learning.
SpringerBriefs in Applied Sciences and Technology, Springer, ISBN: 978-3-319-71489-9, 2018

2017
MiCOMP: Mitigating the Compiler Phase-Ordering Problem Using Optimization Sub-Sequences and Machine Learning.
ACM Trans. Archit. Code Optim., 2017

2016
Compiler autotuning using machine learning techniques.
PhD thesis, 2016

COBAYN: Compiler Autotuning Framework Using Bayesian Networks.
ACM Trans. Archit. Code Optim., 2016

Predictive modeling methodology for compiler phase-ordering.
Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, 2016

An Evaluation of Autotuning Techniques for the Compiler Optimization Problems.
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016

2014
A Bayesian network approach for compiler auto-tuning for embedded processors.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

2013
A framework for Compiler Level statistical analysis over customized VLIW architecture.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013


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