Bram Rooseleer

According to our database1, Bram Rooseleer authored at least 5 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024

2021
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm<sup>2</sup> in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2013
A 40 nm, 454MHz 114 fJ/bit area-efficient SRAM memory with integrated charge pump.
Proceedings of the ESSCIRC 2013, 2013

2012
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link.
IEEE J. Solid State Circuits, 2012

2010
Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2010


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