Ioannis A. Papistas

Orcid: 0000-0002-1771-7011

According to our database1, Ioannis A. Papistas authored at least 17 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2024

2023
DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge.
IEEE J. Solid State Circuits, 2023

2022
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration.
ACM Trans. Design Autom. Electr. Syst., 2022

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm<sup>2</sup> in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
Cost Modeling and Analysis of TSV and Contactless 3D-ICs.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019
Fabrication Cost Analysis for Contactless 3-D ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference.
CoRR, 2019

2018
Design methodologies for heterogeneous 3-D integrated systems.
PhD thesis, 2018

Efficient Modeling of Crosstalk Noise on Power Distribution Networks for Contactless 3-D ICs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Contactless Heterogeneous 3-D ICs for Smart Sensing Systems.
Integr., 2018

2017
Contactless inter-tier communication for heterogeneous 3-D ICs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Crosstalk noise effects of on-chip inductive links on power delivery networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled Interconnects.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs.
Proceedings of the European Conference on Circuit Theory and Design, 2015


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