Florian Zaruba
Orcid: 0000-0002-8194-6521Affiliations:
- Axelera AI, Zürich, Switzerland
According to our database1,
Florian Zaruba
authored at least 27 papers
between 2018 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra.
IEEE Trans. Parallel Distributed Syst., December, 2023
Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
2022
IEEE Trans. Computers, 2022
2021
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads.
IEEE Trans. Computers, 2021
Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores.
IEEE Trans. Computers, 2021
Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing.
IEEE Micro, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range.
Proceedings of the 47th ESSCIRC 2021, 2021
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing.
CoRR, 2020
FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing.
CoRR, 2020
Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads.
CoRR, 2020
Live Demonstration: Exploiting Body-Biasing for Static Corner Trimming and Maximum Energy Efficiency Operation in 22nm FDX Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing.
Proceedings of the IEEE Hot Chips 32 Symposium, 2020
ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020
2019
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI.
CoRR, 2019
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology.
CoRR, 2019
A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and Performance.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018