Harald P. E. Vranken

According to our database1, Harald P. E. Vranken
  • authored at least 29 papers between 1994 and 2018.
  • has a "Dijkstra number"2 of three.

Timeline

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Links

On csauthors.net:

Bibliography

2018
Evaluation of transaction authentication methods for online banking.
Future Generation Comp. Syst., 2018

2017
A Survey of Authentication and Communications Security in Online Banking.
ACM Comput. Surv., 2017

2016
User-friendly Manual Transfer of Authenticated Online Banking Transaction Data - A Case Study that Applies the What You Enter Is What You Sign Transaction Authorization Information Scheme.
Proceedings of the 13th International Joint Conference on e-Business and Telecommunications (ICETE 2016), 2016

The Role of Internet Service Providers in Botnet Mitigation.
Proceedings of the 2016 European Intelligence and Security Informatics Conference, 2016

2014
What You Enter Is What You Sign: Input Integrity in an Online Banking Environment.
Proceedings of the 2014 Workshop on Socio-Technical Aspects in Security and Trust, 2014

An Exercise Assistant for Practical Networking Courses.
Proceedings of the CSEDU 2014, 2014

An Exercise Assistant for Practical Networking and IT Security Courses in Higher Education.
Proceedings of the Computer Supported Education - 6th International Conference, 2014

2013
Counter botnet activities in the Netherlands a study on organisation and effectiveness.
Proceedings of the 8th International Conference for Internet Technology and Secured Transactions, 2013

2011
A distributed virtual computer security lab with central authority.
Proceedings of the Computer Science Education Research Conference, 2011

A Distributed Virtual Computer Security Lab.
Proceedings of the CSEDU 2011, 2011

The Impact of Server Virtualization on ITIL Processes.
Proceedings of the CLOSER 2011, 2011

2008
Experiences with a synchronous virtual classroom in distance education.
Proceedings of the 13th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2008

2006
Fault detection and diagnosis with parity trees for space compaction of test responses.
Proceedings of the 43rd Design Automation Conference, 2006

2004
X-Masking During Logic BIST and Its Impact on Defect Coverage.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Efficient Pattern Mapping for Deterministic Logic BIST.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Impact of Test Point Insertion on Silicon Area and Timing during Layout.
Proceedings of the 2004 Design, 2004

2003
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Enhanced Reduced Pin-Count Test for Full-Scan Design.
J. Electronic Testing, 2002

2001
Application of Deterministic Logic BIST on Industrial Circuits.
J. Electronic Testing, 2001

Enhanced reduced pin-count test for full-scan design.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Circuit partitioning for efficient logic BIST synthesis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Debug Facilities in the TriMedia CPU64 Architecture.
J. Electronic Testing, 2000

Application of deterministic logic BIST on industrial circuits.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

IC Design Validation Using Message Sequence Charts.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Behavior-Preserving Transformations for Design-for-Test.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
TriMedia CPU64 Architecture.
Proceedings of the IEEE International Conference On Computer Design, 1999

1997
Design-For-Debug in Hardware/Software Co-Design.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
Design for Testability in Hardware-Software Systems.
IEEE Design & Test of Computers, 1996

1994
System-Level Testability of Hardware/Software Systems.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994


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