Aristides Efthymiou

According to our database1, Aristides Efthymiou authored at least 18 papers between 1995 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
An error tolerant CAM with nand match-line organization.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2010
Initialization-Based Test Pattern Generation for Asynchronous Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Optimising Self-Timed FPGA Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2008
A Partial Scan Based Test Generation for Asynchronous Circuits.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Synthetic Trace-Driven Simulation of Cache Memory.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2005
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Fast, Parallel Two-Rail Code Checker with Enhanced Testability.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A Low-Power Processor Architecture Optimized forWireless Devices.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
A CAM with mixed serial-parallel comparison for use in low energy caches.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.
Proceedings of the 2004 Design, 2004

Adding Testability to an Asynchronous Interconnect for GALS SoC.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
Adaptive Pipeline Structures fo Speculation Control.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
An adaptive serial-parallel CAM architecture for low-power cache blocks.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Adaptive Pipeline Depth Control for Processor Power-Management.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001
Power Management in the Amulet Microprocessors.
IEEE Des. Test Comput., 2001

1995
Pipelined Memory Shared Buffer for VLSI Switches.
Proceedings of the ACM SIGCOMM 1995 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, Cambridge, MA, USA, August 28, 1995


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