Athanasios Vasilopoulos

Orcid: 0009-0001-9081-6139

According to our database1, Athanasios Vasilopoulos authored at least 22 papers between 1983 and 2025.

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Bibliography

2025
Efficient scaling of large language models with mixture of experts and 3D analog in-memory computing.
Nat. Comput. Sci., January, 2025

Author Correction: Kernel approximation using analogue in-memory computing.
Nat. Mac. Intell., 2025

A framework for analog-digital mixed-precision neural network training and inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

NIMA: Near In-Memory High-Precision Accumulation Unit for Heterogeneous Analog/Digital Deep Learning Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Live Demonstration: Automated DNN Deployment on the IBM HERMES Project Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Analog AI Accelerators for Transformer-based Language Models: Hardware, Workload, and Power Performance.
Proceedings of the IEEE International Memory Workshop, 2025

Multi-Mode Borderguard Controllers for Efficient On-Chip Communication in Heterogeneous Digital/Analog Neural Processing Units.
Proceedings of the Design, Automation & Test in Europe Conference, 2025


2024
Kernel approximation using analogue in-memory computing.
Nat. Mac. Intell., 2024

The Inherent Adversarial Robustness of Analog In-Memory Computing.
CoRR, 2024

Kernel Approximation using Analog In-Memory Computing.
CoRR, 2024

Learning-to-learn enables rapid learning with phase-change memory-based in-memory computing.
CoRR, 2024

Improving the Accuracy of Analog-Based In-Memory Computing Accelerators Post-Training.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Programming Weights to Analog In-Memory Computing Cores by Direct Minimization of the Matrix-Vector Multiplication Error.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

Gradient descent-based programming of analog in-memory computing cores.
CoRR, 2023

2022
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.
CoRR, 2022

2006
A 1-V, 5.5-GHz, CMOS LNA With Multiple Magnetic Feedback.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A Low-Power Wideband Reconfigurable Integrated Active-RC Filter With 73 dB SFDR.
IEEE J. Solid State Circuits, 2006

A low-voltage CMOS LNA with multiple magnetic feedback for WLAN applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Calculating distortion in active CMOS mixers using Volterra series.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

1983
Generating correlated random variables for quality control applications.
Proceedings of the 16th Annual Symposium on Simulation, 1983


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