Chen Sun

  • Intel Corporation, USA
  • Ayar Labs, Emeryville, CA, USA
  • University of California, Berkeley, CA, USA (former)
  • Massachusetts Institute of Technology, Cambridge, MA, USA (PhD 2015)

According to our database1, Chen Sun authored at least 28 papers between 2010 and 2023.

Collaborative distances:



In proceedings 
PhD thesis 




Driving Compute Scale-out Performance with Optical I/O Chiplets in Advanced System-in-Package Platforms.
Proceedings of the 35th IEEE Hot Chips Symposium, 2023



TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O.
IEEE Micro, 2020

A Differential Optical Receiver With Monolithic Split-Microring Photodetector.
IEEE J. Solid State Circuits, 2019

TeraPHY: A High-Density Electronic-Photonic Chiplet for Optical I/O from a Multi-Chip Module.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

A Bandwidth-Dense, Low Power Electronic-Photonic Platform and Architecture for Multi-Tbps Optical I/O.
Proceedings of the European Conference on Optical Communication, 2018


WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation Disaggregated Cloud Data Centers.
Proceedings of the 25th IEEE Annual Symposium on High-Performance Interconnects, 2017

A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning.
IEEE J. Solid State Circuits, 2016

A 12Gb/s, 8.6µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI process.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Silicon-photonics for very large scale integrated systems.
PhD thesis, 2015

Single-chip microprocessor that communicates directly using light.
Nat., 2015

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS.
IEEE J. Solid State Circuits, 2015

A 45nm SOI monolithic photonics chip-to-chip link with bit-statistics-based resonant microring thermal tuning.
Proceedings of the Symposium on VLSI Circuits, 2015

An ultra low power 3D integrated intra-chip silicon electronic-photonic link.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

DELPHI: a framework for RTL-based architecture design evaluation using DSENT models.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform.
Proceedings of the ESSCIRC Conference 2015, 2015

A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process.
Proceedings of the Symposium on VLSI Circuits, 2014

Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators.
Proceedings of the ESSCIRC 2014, 2014

A 1.23pJ/b 2.5Gb/s monolithically integrated optical carrier-injection ring modulator and all-digital driver circuit in commercial 45nm SOI.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System Using Real Application Workloads.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Addressing link-level design tradeoffs for integrated photonic interconnects.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Re-architecting DRAM memory systems with monolithically integrated silicon photonics.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010