Chenyang Zhao

According to our database, Chenyang Zhao authored at least 10 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Light-CIM: A Lightweight ADC/DAC-Fewer RRAM CIM DNN Accelerator With Fully Analog Tiles and Nonideality-Aware Algorithm for Consumer Electronics.

Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2025

2024

A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm² 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications.

Chenyang Zhao, Jinbei Fang, Xiaoli Huang, Deyang Chen, Zhiwang Guo, Jingwen Jiang, Jiawei Wang, Jianguo Yang, Jun Han, Peng Zhou, Xiaoyong Xue, Xiaoyang Zeng

IEEE J. Solid State Circuits, October, 2024

A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications.

Lizhou Wu, Chenyang Zhao, Jingbo Wang, Xueru Yu, Shoumian Chen, Chen Li, Jun Han, Xiaoyong Xue, Xiaoyang Zeng

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications.

Jingwen Jiang, Keji Zhou, Jinhao Liang, Fengshi Tian, Chenyang Zhao, Jianguo Yang, Xiaoyong Xue, Xiaoyang Zeng

IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices.

Zhiwang Guo, Deyang Chen, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Yixuan Liu, Haidong Tian, Xiankui Xiong, Keji Zhou, Xiaoyong Xue, Qi Liu, Xiaoyang Zeng

IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application.

Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications.

Deyang Chen, Zhiwang Guo, Jinbei Fang, Chenyang Zhao, Jingwen Jiang, Keji Zhou, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng

IEEE Trans. Circuits Syst. II Express Briefs, 2023

2022

A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output.

Keji Zhou, Xinru Jia, Chenyang Zhao, Xumeng Zhang, Guangjian Wu, Chen Mu, Haozhe Zhu, Yanting Ding, Chixiao Chen, Xiaoyong Xue, Xiaoyang Zeng, Qi Liu

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.

Keji Zhou, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Deyang Chen, Yujie Huang, Ming-e Jing, Jun Han, Haidong Tian, Xiankui Xiong, Qi Liu, Xiaoyong Xue, Xiaoyang Zeng

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications.

Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Zhiwang Guo, Xiaoyong Xue, Xiaoyang Zeng

Proceedings of the 14th IEEE International Conference on ASIC, 2021