Dae-Han Kim

According to our database, Dae-Han Kim authored at least 6 papers between 2006 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

Demagnetization Analysis of Interior Permanent Magnet Synchronous Motors Under Realistic Vehicle Driving Conditions.

Yun-Jin Yang, Dae-Han Kim, Yong-Min You

IEEE Access, 2026

2016

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate.

Woopyo Jeong, Jae-Woo Im, Doo-Hyun Kim, Sangwan Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, Hyun Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jinho Ryu, Sang-Won Shim, Kyung-Tae Kang, Jeong-Don Ihm, In-Mo Kim, Doosub Lee, Ji-Ho Cho, Moosung Kim, Jae-hoon Jang, Sang-Won Hwang, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi

IEEE J. Solid State Circuits, 2016

2015

Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.

Ki-Tae Park, Sangwan Nam, Dae-Han Kim, Pansuk Kwak, Doosub Lee, Yoon-Hee Choi, Myung-Hoon Choi, Dong-Hun Kwak, Doo-Hyun Kim, Minsu Kim, Hyun Wook Park, Sang-Won Shim, Kyung-Min Kang, Sang-Won Park, Kangbin Lee, Hyun-Jun Yoon, Kuihan Ko, Dong-Kyo Shim, Yang-Lo Ahn, Jinho Ryu, Donghyun Kim, Kyunghwa Yun, Joonsoo Kwon, Seunghoon Shin, Dae-Seok Byeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Jeong-Hyuk Choi, Kinam Kim

IEEE J. Solid State Circuits, 2015

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate.

Jae-Woo Im, Woopyo Jeong, Doo-Hyun Kim, Sangwan Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, Hyun Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jinho Ryu, Sang-Won Shim, Kyung-Tae Kang, Sung-Ho Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doosub Lee, Ji-Ho Cho, Ohsuk Kwon, Ji-Sang Lee, Moosung Kim, Sang-Hyun Joo, Jae-hoon Jang, Sang-Won Hwang, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming.

Ki-Tae Park, Jin-Man Han, Dae-Han Kim, Sangwan Nam, Kihwan Choi, Minsu Kim, Pansuk Kwak, Doosub Lee, Yoon-Hee Choi, Kyung-Min Kang, Myung-Hoon Choi, Dong-Hun Kwak, Hyun Wook Park, Sang-Won Shim, Hyun-Jun Yoon, Doo-Hyun Kim, Sang-Won Park, Kangbin Lee, Kuihan Ko, Dong-Kyo Shim, Yang-Lo Ahn, Jeunghwan Park, Jinho Ryu, Donghyun Kim, Kyunghwa Yun, Joonsoo Kwon, Seunghoon Shin, Dongkyu Youn, Won-Tae Kim, Taehyun Kim, Sung-Jun Kim, Sungwhan Seo, Hyunggon Kim, Dae-Seok Byeon, Hyang-Ja Yang, Moosung Kim, Myong-Seok Kim, Jinseon Yeon, Jae-hoon Jang, Han-Soo Kim, Woonkyung Lee, Duheon Song, Sungsoo Lee, Kyehyun Kyung, Jeong-Hyuk Choi

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2006

Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model.

Young-Gu Kim, Sang-Hoon Lee, Dae-Han Kim, Jae-Woo Im, Sung-Eun Yu, Dae-Wook Kim, Young-Kwan Park, Jeong-Taek Kong

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006