Dae-Seok Byeon

Affiliations:
  • Samsung, Seoul, South Korea


According to our database1, Dae-Seok Byeon authored at least 19 papers between 2002 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2022
Cell Operation Technologies to Overcome Scale-down Issues in 3D NAND Flash Memory.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

2021
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage.
IEEE J. Solid State Circuits, 2021


2020
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020


2019

2018
A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory.
IEEE J. Solid State Circuits, 2018


2017
256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers.
IEEE J. Solid State Circuits, 2017


2016
A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate.
IEEE J. Solid State Circuits, 2016



2015
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.
IEEE J. Solid State Circuits, 2015



2014

2003
A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications.
IEEE J. Solid State Circuits, 2003

2002
High-performance 1-Gb-NAND flash memory with 0.12-μm technology.
IEEE J. Solid State Circuits, 2002


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