Jeong-Hyuk Choi

According to our database¹, Jeong-Hyuk Choi authored at least 8 papers between 2003 and 2016.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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Bibliography

2016

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2003

A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

Jeong-Hyuk Choi

Timeline

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