Jacopo Franco

According to our database1, Jacopo Franco authored at least 45 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Degradation mechanisms and lifetime assessment of Ge Vertical PIN photodetectors.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Interpretation and modelling of dynamic-RON kinetics in GaN-on-Si HEMTs for mm-wave applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Significant Enhancement of HCD and TDDB in CMOS FETs by Mechanical Stress.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
A BSIM-Based Predictive Hot-Carrier Aging Compact Model.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Physics-based device aging modelling framework for accurate circuit reliability assessment.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

The properties, effect and extraction of localized defect profiles from degraded FET characteristics.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

CV Stretch-Out Correction after Bias Temperature Stress: Work-Function Dependence of Donor-/Acceptor-Like Traps, Fixed Charges, and Fast States.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper.
Proceedings of the International Conference on IC Design and Technology, 2021

2020
Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

On the impact of mechanical stress on gate oxide trapping.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Array-Based Statistical Characterization of CMOS Degradation Modes and Modeling of the Time-Dependent Variability Induced by Different Stress Patterns in the {V<sub>G</sub>, V<sub>D</sub>} bias space.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
Comphy - A compact-physics framework for unified modeling of BTI.
Microelectron. Reliab., 2018

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability.
Microelectron. Reliab., 2018

Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Hot electron and hot hole induced degradation of SiGe p-FinFETs studied by degradation maps in the entire bias space.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Self-heating-aware CMOS reliability characterization using degradation maps.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2016

A drift-diffusion-based analytic description of the energy distribution function for hot-carrier degradation in decananometer nMOSFETs.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocess. Microsystems, 2015

Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Origins and implications of increased channel hot carrier variability in nFinFETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

ESD characterization of planar InGaAs devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

The defect-centric perspective of device and circuit reliability - From individual defects to circuits.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Experimental evidences and simulations of trap generation along a percolation path.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Characterization and simulation methodology for time-dependent variability in advanced technologies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Characterization and modeling of charge trapping: From single defects to devices.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Impact of Off State Stress on advanced high-K metal gate NMOSFETs.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2012
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Defect-centric perspective of time-dependent BTI variability.
Microelectron. Reliab., 2012

BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic.
Microelectron. Reliab., 2012

Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011


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