Qiaoyan Yu

Nishanth Goud Chennagouni

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

2023

Hardware Security Risks and Threat Analyses in Advanced Manufacturing Industry.

[BibT_eX]

[DOI]

Joshua Calzadillas

ACM Trans. Design Autom. Electr. Syst., September, 2023

Securing Approximate Computing Systems via Obfuscating Approximate-Precise Boundary.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

A Circuit-Level Solution for Secure Temperature Sensor.

[BibT_eX]

[DOI]

Sensors, 2023

Supply reliability analysis of natural gas pipeline network based on demand-side economic loss risk.

[BibT_eX]

[DOI]

Reliab. Eng. Syst. Saf., 2023

Attack-Resilient Temperature Sensor Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

AHD-LAM: A New Mitigation Method against Voltage-Drop Attacks in Multi-tenant FPGAs.

[BibT_eX]

[DOI]

Nishanth Goud Chennagouni

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

A Hybrid Neural Network for Simultaneous Multi-Attack Detection in Sensor Networks.

[BibT_eX]

[DOI]

Wei Lu

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022

DPReDO: Dynamic Partial Reconfiguration enabled Design Obfuscation for FPGA Security.

[BibT_eX]

[DOI]

Nishanth Goud Chennagouni

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Challenges of Securing Low-Power LoRaWAN Devices Deployed in Advanced Manufacturing.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Security Threats and Countermeasure Deployment Using Partial Reconfiguration in FPGA CAD Tools.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

Session details: Session 6A: Special Session -1: Machine Learning and Hardware Attacks.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Hardware Security in Advanced Manufacturing.

[BibT_eX]

[DOI]

Joshua Calzadillas

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Optimal pressure sensor locations in smart insoles for heel-strike and toe-off detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

Towards Securing Approximate Computing Systems: Security Threats and Attack Mitigation.

[BibT_eX]

[DOI]

Landon Buell

Proceedings of the Approximate Computing, 2022

2021

Security Threat Analyses and Attack Models for Approximate Computing Systems: From Hardware and Micro-architecture Perspectives.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

Explainable fault diagnosis of gas-liquid separator based on fully convolutional neural network.

[BibT_eX]

[DOI]

Comput. Chem. Eng., 2021

Boosting SMT solver performance on mixed-bitwise-arithmetic expressions.

[BibT_eX]

[DOI]

Proceedings of the PLDI '21: 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2021

Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

New Security Threats on FPGAs: From FPGA Design Tools Perspective.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Analysis of Attack Surfaces and Practical Attack Examples in Open Source FPGA CAD Tools.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

Guest Editor's Introduction: Special Section on Reliability-Aware Design and Analysis Methods for Digital Systems: From Gate to System Level.

[BibT_eX]

[DOI]

Antonio Miele

Maria K. Michael

IEEE Trans. Emerg. Top. Comput., 2020

Comprehensive Analysis on Hardware Trojans in 3D ICs: Characterization and Experimental Impact Assessment.

[BibT_eX]

[DOI]

SN Comput. Sci., 2020

Improving power analysis attack resistance using intrinsic noise in 3D ICs.

[BibT_eX]

[DOI]

Integr., 2020

FTAI: Frequency-based Trojan-Activity Identification Method for 3D Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

ADobf: Obfuscated Detection Method against Analog Trojans on I<sup>2</sup>C Master-Slave Interface.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Invariance Checking Based Trojan Detection Method for Three-Dimensional Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Can We Securely Use Approximate Computing?

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

New Replay Attacks on ZigBee Devices for Internet-of-Things (IoT) Applications.

[BibT_eX]

[DOI]

Mohammad Shafeul Wara

Proceedings of the 2020 IEEE International Conference on Embedded Software and Systems, 2020

Blurring Boundaries: A New Way to Secure Approximate Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Security Threats and Countermeasures for Approximate Arithmetic Computing.

[BibT_eX]

[DOI]

Timothy Kammerer

Dongpeng Xu

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

SRASA: a Generalized Theoretical Framework for Security and Reliability Analysis in Computing Systems.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2019

Modeling Hardware Trojans in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Emerging Applications of 3D Integration and Approximate Computing in High-Performance Computing Systems: Unique Security Vulnerabilities.

[BibT_eX]

[DOI]

Ranuli Abeysinghe

Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

Security Threats in Approximate Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

An Orthogonal Algorithm for Key Management in Hardware Obfuscation.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018

Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process.

[BibT_eX]

[DOI]

Microelectron. J., 2018

Exploiting Principle of Moving Target Defense to Secure FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Investigating Reliability and Security of Integrated Circuits and Systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Securing FPGA-based obsolete component replacement for legacy systems.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

FPGA-oriented moving target defense against security threats from malicious FPGA tools.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

A Survey on Energy Efficiency Techniques for Secure Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Exploiting PDN noise to thwart correlation power analysis attacks in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018

2017

A hardened network-on-chip design using runtime hardware Trojan mitigation methods.

[BibT_eX]

[DOI]

Integr., 2017

Exploiting hardware obfuscation methods to prevent and detect hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A low-cost masquerade and replay attack detection method for CAN in automobiles.

[BibT_eX]

[DOI]

Mohammad Raashid Ansari

W. Thomas Miller III

Chenghua She

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Analyzing security vulnerabilities of three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Mitigating Control Flow Attacks in Embedded Systems with Novel Built-in Secure Register Bank.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Security Threats and Countermeasures in Three-Dimensional Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Welcome Message.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016

A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack.

[BibT_eX]

[DOI]

J. Electron. Test., 2016

PSS4: Four-Phase Shifted Sinusoid Symbol Signaling for High Speed I/O interconnects.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2016

DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation.

[BibT_eX]

[DOI]

Yuejun Zhang

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Hardware security assurance in emerging IoT applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Transistor-level camouflaged logic locking method for monolithic 3D IC security.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Foreword.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Assessing CPA resistance of AES with different fault tolerance mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Strengthening SIMON Implementation Against Intelligent Fault Attacks.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2015

Exploiting state obfuscation to detect hardware trojans in NoC network interfaces.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Investigating power characteristics of memristor-based logic gates and their applications in a security primitive.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Fault-tolerant methods for a new lightweight cipher SIMON.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Investigation of single-event upsets in dynamic logic based flip-flops.

[BibT_eX]

[DOI]

Patrick Nsengiyumva

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

IntelliCAN: Attack-resilient Controller Area Network (CAN) for secure automobiles.

[BibT_eX]

[DOI]

Mohammad Raashid Ansari

Shucheng Yu

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Advanced VLSI Architecture Design for Emerging Digital Systems.

[BibT_eX]

[DOI]

VLSI Design, 2014

Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic.

[BibT_eX]

[DOI]

Wafi Danesh

VLSI Design, 2014

A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients.

[BibT_eX]

[DOI]

J. Electron. Test., 2014

Systematic analyses for latching probability of single-event transients.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A new fault injection method for evaluation of combining SEU and SET effects on circuit reliability.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A novel signaling technique for high-speed wireline backplane transceiver: Four phase-shifted sinusoid symbol (PSS-4).

[BibT_eX]

[DOI]

Kejun Wu

Peng Liu

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Addressing network-on-chip router transient errors with inherent information redundancy.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

A fully integrated video digital-to-analog converter with minimized gain error.

[BibT_eX]

[DOI]

Tao Zhang

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Collaborative error control method for sequential logic circuits.

[BibT_eX]

[DOI]

Drew Stock

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A novel energy-efficient serializer design method for gigascale systems.

[BibT_eX]

[DOI]

Kejun Wu

Peng Liu

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Exploiting error control approaches for Hardware Trojans on Network-on-Chip links.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

Dual-Layer Adaptive Error Control for Network-on-Chip Links.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Fine-grained splitting methods to address permanent errors in Network-on-Chip links.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Transient error management for partially adaptive router in network-on-chip (NoC).

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A Dual-Layer Method for Transient and Permanent Error Co-Management in NoC Links.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A comprehensive Networks-on-Chip simulator for error control explorations.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

Adaptive Voltage Control for Energy-Efficient NoC Links.

[BibT_eX]

[DOI]

Proceedings of the Low Power Networks-on-Chip., 2011

2010

A Flexible Parallel Simulator for Networks-on-Chip With Error Control.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2010, 2010

Error control integration scheme for reliable NoC.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

A simulator for ballistic nanostructures in a 2-D electron gas.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2009

Adaptive error control for nanometer scale network-on-chip links.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Configurable error correction for multi-wire errors in switch-to-switch SOC links.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Adaptive error control for reliable systems-on-chip.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

A ballistic nanoelectronic device simulator.

[BibT_eX]

[DOI]

Dennis Huo

Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

2006

Cell Ratio Bounds for Reliable SRAM Operation.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Energy-delay minimization in nanoscale domino logic.

[BibT_eX]

[DOI]

Bo Fu