Qiaoyan Yu

According to our database1, Qiaoyan Yu authored at least 61 papers between 2006 and 2019.

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Bibliography

2019
A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS.
IEEE Trans. VLSI Syst., 2019

Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense.
IEEE Trans. VLSI Syst., 2019

Security Threats in Approximate Computing Systems.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs.
IEEE Trans. on Circuits and Systems, 2018

Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process.
Microelectronics Journal, 2018

Exploiting Principle of Moving Target Defense to Secure FPGA Systems.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Investigating Reliability and Security of Integrated Circuits and Systems.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Securing FPGA-based obsolete component replacement for legacy systems.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

FPGA-oriented moving target defense against security threats from malicious FPGA tools.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

A Survey on Energy Efficiency Techniques for Secure Computing Systems.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Exploiting PDN noise to thwart correlation power analysis attacks in 3D ICs.
Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018

2017
A hardened network-on-chip design using runtime hardware Trojan mitigation methods.
Integration, 2017

A low-cost masquerade and replay attack detection method for CAN in automobiles.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Analyzing security vulnerabilities of three-dimensional integrated circuits.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Mitigating Control Flow Attacks in Embedded Systems with Novel Built-in Secure Register Bank.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Security Threats and Countermeasures in Three-Dimensional Integrated Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack.
J. Electronic Testing, 2016

PSS4: Four-Phase Shifted Sinusoid Symbol Signaling for High Speed I/O interconnects.
Computers & Electrical Engineering, 2016

DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Hardware security assurance in emerging IoT applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Transistor-level camouflaged logic locking method for monolithic 3D IC security.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Foreword.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Assessing CPA resistance of AES with different fault tolerance mechanisms.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Strengthening SIMON Implementation Against Intelligent Fault Attacks.
Embedded Systems Letters, 2015

Fault-tolerant methods for a new lightweight cipher SIMON.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Investigation of single-event upsets in dynamic logic based flip-flops.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

IntelliCAN: Attack-resilient Controller Area Network (CAN) for secure automobiles.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
Advanced VLSI Architecture Design for Emerging Digital Systems.
VLSI Design, 2014

Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic.
VLSI Design, 2014

A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients.
J. Electronic Testing, 2014

Systematic analyses for latching probability of single-event transients.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A new fault injection method for evaluation of combining SEU and SET effects on circuit reliability.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A novel signaling technique for high-speed wireline backplane transceiver: Four phase-shifted sinusoid symbol (PSS-4).
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Addressing network-on-chip router transient errors with inherent information redundancy.
ACM Trans. Embedded Comput. Syst., 2013

A fully integrated video digital-to-analog converter with minimized gain error.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Collaborative error control method for sequential logic circuits.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A novel energy-efficient serializer design method for gigascale systems.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Exploiting error control approaches for Hardware Trojans on Network-on-Chip links.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Dual-Layer Adaptive Error Control for Network-on-Chip Links.
IEEE Trans. VLSI Syst., 2012

Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Fine-grained splitting methods to address permanent errors in Network-on-Chip links.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Transient error management for partially adaptive router in network-on-chip (NoC).
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Dual-Layer Method for Transient and Permanent Error Co-Management in NoC Links.
IEEE Trans. on Circuits and Systems, 2011

A comprehensive Networks-on-Chip simulator for error control explorations.
Proceedings of the NOCS 2011, 2011

Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration.
Proceedings of the NOCS 2011, 2011

Adaptive Voltage Control for Energy-Efficient NoC Links.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
A Flexible Parallel Simulator for Networks-on-Chip With Error Control.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip.
Proceedings of the NOCS 2010, 2010

Error control integration scheme for reliable NoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A simulator for ballistic nanostructures in a 2-D electron gas.
JETC, 2009

Adaptive error control for nanometer scale network-on-chip links.
IET Computers & Digital Techniques, 2009

Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Configurable error correction for multi-wire errors in switch-to-switch SOC links.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Adaptive error control for reliable systems-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
A ballistic nanoelectronic device simulator.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

2006
Cell Ratio Bounds for Reliable SRAM Operation.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Energy-delay minimization in nanoscale domino logic.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006


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