Alessandro Veronesi

Orcid: 0009-0000-1159-4463

According to our database1, Alessandro Veronesi authored at least 12 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Cross-Layer Reliability Analysis of Slimmable Neural Networks under Permanent Faults.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026


2025

Special Session Paper: Simulation Methodologies and Experiments for Reliability Analysis of Devices in Radiation Harsh Environments.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2025

EMBER: A Cycle-based Framework for Early-Stage Reliability Assessment in Parametric RTL Designs.
Proceedings of the 34th IEEE Asian Test Symposium, 2025

2024
An Ultra-Low Cost and Multicast-Enabled Asynchronous NoC for Neuromorphic Edge Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

Reliability Assessment of Large DNN Models: Trading Off Performance and Accuracy.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space.
Proceedings of the IEEE European Test Symposium, 2024

2023
Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins.
Proceedings of the High Performance Computing, 2023

2022
Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2020
Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform.
Proceedings of the VLSI-SoC: Design Trends, 2020


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